A bus system is proposed, which includes M (M is a natural number) master ports, N (N is a natural number) slave ports, a bus, A (A is a natural number) masters, B (B is a natural number) salves, and an internal memory. The bus system includes P (P is a natural number, P≤M) master ports, a traffic monitoring unit, Q (Q is a natural number, Q≤N) slaves, a port traffic monitoring unit, and a memory clock scaling unit. Accordingly, in a system-on-chip using a low-power processor, a memory clock of an internal memory connected to a plurality of slave ports is scaled so as to distribute bus traffic.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A bus system comprising: a bus with M master ports and N slave ports connected thereto, where M is a natural number and N is a natural number; A masters connected to the M master ports, respectively, where A is a natural number; B slaves connected to the N slave ports, respectively, where B is a natural number; an internal memory controller connected to C slave ports that are selected according to predetermined priority among the N slave ports, where C is a natural number and C≤N; and a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller, wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, and the internal memory writes data based on a memory clock, wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.
2. The bus system of claim 1 , wherein the bus is configured in such a way that the M master ports as a horizontal axis and the N slave ports as a vertical axis are connected in a matrix form.
3. The bus system of claim 1 , further comprising a port traffic monitoring unit connected to P mater ports that are selected according to predetermined priority among the M master ports, connected Q slave ports that are selected according to predetermined priority among the N slave ports, and configured to monitor at least one port among the M master ports and the Q slave ports, where P is a natural number, P≤M, Q is a natural number, and Q≤N.
4. The bus system of claim 3 , wherein the port traffic monitoring unit monitors traffic of at least port among the P master ports and the Q slave ports using at least one of a weighting and number of command signals.
5. The bus system of claim 1 , further comprising a port traffic monitoring unit connected to P mater ports that are selected according to predetermined priority among the M master ports, connected Q slave ports that are selected according to predetermined priority among the N slave ports, and configured to monitor at least one port among the M master ports and the Q slave ports, where P is a natural number, P≤M, Q is a natural number, and Q≤N wherein the memory clock scaling unit scales the memory clock using traffic of a port monitored by the port traffic monitoring unit.
6. The bus system of claim 1 , wherein the bus is based on an advanced high performance bus (AHB) interface.
7. The bus system of claim 1 , wherein the internal memory is a static random access memory (SRAM).
8. A memory time-sharing apparatus comprising: a bus with M master ports and N slave ports connected thereto where M is a natural number and N is a natural number; A masters connected to the M master ports, respectively, where A is a natural number; B slaves connected to the N slave ports, respectively, where B is a natural number; an internal memory controller connected to C slave ports that are selected according to predetermined priority among the N slave ports, where C is a natural number, and C≤N; a multiplexer connected to the internal memory controller; a memory unit connected to the multiplexer and configured to write data; and a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller, wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, the internal memory controller controls the commands issued by the A masters according to an order based on the memory clock, and the multiplexer selects one slave port according to predetermined priority among C slave ports connected to the internal memory controller using a multiplexer selection signal, the multiplexer selection signal being operated based on a selection signal clock, wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.
9. The memory time-sharing apparatus of claim 8 , wherein the internal memory controller comprises C separate address areas and the C address areas and the C slave ports are connected, respectively.
10. The memory time-sharing apparatus of claim 8 , wherein the number of slave ports connected to the internal memory controller is 2.
11. The memory time-sharing apparatus of claim 10 , wherein the selection signal clock is the same as the bus clock and the memory clock is twice the bus clock.
12. The memory time-sharing apparatus of claim 8 , wherein the number of salve ports connected to the internal memory controller is 4.
13. The memory time-sharing apparatus of claim 12 , wherein the selection signal clock is twice the bus clock and the memory clock is four times the bus clock.
14. A memory time-sharing apparatus comprising: a bus with M master ports and N slave ports connected thereto where M is a natural number and N is a natural number; A masters connected to the M master ports, respectively, where A is a natural number; B slaves connected to the N slave ports, respectively, where B is a natural number; an internal memory controller connected to C slave ports that are selected according to predetermined priority among the N slave ports, where C is a natural number and C≤N; C multiplexers connected to the internal memory controller and D slave ports for time-sharing among the N slave ports, where D is a natural number and C+D≤N; C memory units connected to the C multiplexers, respectively and to configured to write data; and a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller, wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, the internal memory controller controls the commands issued by the A masters according to an order based on the memory clock, and the C multiplexers select one slave port according to predetermined priority among the C slave ports connected to the internal memory controllers using each multiplexer selection signal, the multiplexer selection signal being operated based on a selection signal clock, wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.
15. The memory time-sharing apparatus of claim 14 , wherein the internal memory controller comprises a plurality of separate address areas, the plurality of address areas have address areas pointing the A masters, and each of the address areas pointing the A maters has an address area pointing the C slaves.
16. The memory time-sharing apparatus of claim 14 , wherein: the internal memory controller comprises C separate address areas; and the C address areas are connected to the C slave ports, respectively, one of the C address areas and the D slave ports for time-sharing are connected to an input of one of the C multiplexers, and outputs of the C multiplexers are connected to the C memory units, respectively.
17. The memory time-sharing apparatus of claim 16 , wherein C address areas included in the internal memory controller are separated using some of bits included in an address.
18. A memory time-sharing apparatus comprising: a bus with M master ports and N slave ports connected thereto where M is a natural number, N is a natural number, and N≥5; A masters connected to the M master ports, respectively, where A is a natural number; B slaves connected to the N slave ports, respectively, where B is a natural number; an internal memory controller connected to four slave ports that are selected according to predetermined priority among the N slave ports; four multiplexers connected to the internal memory controller and one slave port for time-sharing among the N slave ports; four memory units connected to the four multiplexers and configured to write data; and a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller, wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, the internal memory controller controls the commands issued by the A masters according to an order based on the memory clock, and the four multiplexers select one slave port according to predetermined priority among the four slave ports connected to the internal memory controller using each multiplexer selection signal, the multiplexer selection signal being operated based on a selection signal clock, wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.
19. The memory time-sharing apparatus of claim 18 , wherein: the internal memory controller comprises four separate address areas; and the four address areas are connected to the four slave ports, respectively, one of the four address areas and the one slave port for time-sharing are connected to an input of one of the four multiplexers, and outputs of the four multiplexers are connected to the four memory units, respectively.
20. The memory time-sharing apparatus of claim 19 , wherein the selection signal clock is the same as the bus clock and the memory clock is twice the bus clock.
21. A memory time-sharing apparatus comprising: a bus with M master ports and N slave ports connected thereto where M is a natural number, N is a natural number, and N≥5; A masters connected to the M master ports, respectively, where A is a natural number; B slaves connected to the N slave ports, respectively, where B is a natural number; an internal memory controller connected to two slave ports that are selected according to predetermined priority among the N slave ports; two multiplexers connected to the internal memory controller and three slave ports for time-sharing among the N slave ports; two memory units connected to the two multiplexers, respectively, and configured to write data; and a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller, wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, the internal memory controller controls the commands issued by the A masters according to an order based on the memory clock, and the two multiplexers select one slave port according to predetermined priority among two slave ports connected to the internal memory controllers using each multiplexer selection signal, the multiplexer selection signal being operated based on a selection signal clock, wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.
22. The memory time-sharing apparatus of claim 21 , wherein: the internal memory controller comprises two separate address areas; and the two address areas are connected to the two slave ports, respectively, one of the two address areas and the three slave ports for time-sharing are connected to an input of one of the two multiplexers, and outputs of the two multiplexers are connected to the two memory units, respectively.
23. The memory time-sharing apparatus of claim 22 , wherein the selection signal clock is twice the bus clock and the memory clock is four times the bus clock.
24. A memory time-sharing apparatus comprising a memory address map having plurality of address areas using some of bits included in an address, wherein some of the plurality of address areas are allocated an address area to be used as an internal memory, and the address area to be used as the internal memory has an address area pointing a master port and an address area pointing a slave port, and wherein a memory clock of the internal memory is scaled based on the number of slave ports connected to the internal memory, and wherein the memory clock of the internal memory is scaled to S times a bus clock, where S is a natural number.
25. A memory time-sharing method for distributing bus traffic by a bus system comprising a bus for connection of M master ports and N slave ports and a memory connected to C slave ports among the N slave ports, where M is a natural number, N is a natural number, C is a natural number, and C≤N, the method comprising: setting a bus clock for operating the bus and a memory clock for operating the memory; selecting E slave ports among the C slave ports, where E is a natural number, and E≤C; scaling the memory clock according to the E slave ports, wherein the memory clock is scaled to S times the bus clock, where S is a natural number; and activating the E slave ports.
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July 10, 2017
May 12, 2020
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