A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A ReRAM cell comprising: a first bitline; a second bitline; an output node; a pullup ReRAM device having an ion source end and a solid electrolyte end, the solid electrolyte end of the pullup ReRAM device coupled to the first bitline; a first access transistor coupled between the ion source end of the pullup ReRAM device and the output node; a pulldown ReRAM device having an ion source end and a solid electrolyte end, the ion source end of the pullup ReRAM device coupled to the second bitline; and a second access transistor coupled between the solid electrolyte end of the pulldown ReRAM device and the output node.
2. The ReRAM cell of claim 1 further comprising a programming transistor coupled between the output node and a wordline source node, the programming transistor having a gate coupled to a wordline associated with the memory cell.
3. The ReRAM cell of claim 1 wherein: the first access transistor comprises a p-channel transistor; and the second access transistor comprises an n-channel transistor.
4. The ReRAM cell of claim 1 wherein the programming transistor comprises an n-channel transistor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 24, 2019
May 12, 2020
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