The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28).The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: a first electrode, a second electrode and an active portion for changing a conductive state, wherein the active portion is positioned between a first face of the first electrode and a first face of the second electrode, the first electrode comprises an upper portion forming the first face of the first electrode, at least one of the upper portion and the active portion comprises a porous layer, and the porous layer is obtained from p- or n-doped silicon.
2. The memory device according to claim 1 , wherein the porous layer is comprised in the upper portion, the porous layer is in contact with the active portion, and the porous layer is located on a base portion of the first electrode, at least one pore of the porous layer being at least partially filled with an electrically conductive material configured to establish electric continuity between the base portion of the first electrode and the active portion.
3. The memory device according to claim 2 , wherein the electrically conductive material completely fills at least one pore.
4. The memory device according to claim 2 , wherein the porous layer has an electrical resistivity greater than or equal to that of the electrically conductive material.
5. The memory device according to claim 2 , wherein the electrically conductive material is titanium nitride.
6. The memory device according to claim 2 , wherein the porous layer is made of silicon dioxide.
7. The memory device according to claim 6 , wherein the silicon dioxide is obtained via oxidation of the p- or n-doped silicon.
8. The memory device according to claim 1 , wherein the porous layer is comprised in the active portion and the porous layer is in contact with at least one of the first face of the first electrode and the first face of the second electrode.
9. The memory device according to claim 8 , wherein the pores of the porous layer are at least partly under vacuum, or filled with air or filled with a material that is more electrically insulating than a material of the porous layer and/or of a dielectric nature.
10. The memory device according to claim 8 , wherein the active portion comprises, between the porous layer and the second electrode, a second layer more electrically insulating than the porous layer.
11. The memory device according to claim 10 , wherein the second layer is made of an oxide of a material of the porous layer.
12. The memory device according to claim 8 , wherein a material of the porous layer forms a material for changing a conductive state.
13. The memory device according to claim 1 , wherein the porous layer is a semi-insulating material.
14. The memory device according to claim 1 , wherein a size of pores of the porous layer is less than 10 nm.
15. The memory device according to claim 1 , wherein a thickness dimension of the porous layer is less than 100 nm.
16. The memory device according to claim 1 , wherein a size of pores of the porous layer is greater than or equal to 2 nm.
17. A method for manufacturing the memory device of claim 1 , the method comprising: (i) forming the first electrode; (ii) forming the active portion, which has a face in contact with the first face of the first electrode; and (iii) forming the second electrode in contact with another face of the active portion, wherein the porous layer is formed in at least one of the upper portion and the active portion.
18. The method according to claim 17 , wherein the forming (i) comprises (i-i) forming an upper portion, which forms the first face of the first electrode, the forming (i-i) comprising: forming the porous layer, which is in contact with the active layer and located on a base portion of the first electrode; and at least partial filling at least one pore of the porous layer with an electrically conductive material configured to establish electric continuity between the base portion of the first electrode and the active layer.
19. The method according to claim 18 , wherein the at least partial filling is configured to completely fill at least one pore.
20. The method according to claim 18 , wherein a material of the porous layer is chosen to be more electrically resistive than the electrically conductive material.
21. The method according to claim 18 , wherein the at least partial filling comprises depositing the electrically conducive material on the porous layer and then removing a portion of the electrically conductive material deposited on a surface of the porous layer.
22. The method according to claim 17 , wherein the forming (ii) comprises forming a porous layer in contact with the first electrode.
23. The method according to claim 22 , wherein a material of the porous layer forms a material for changing a conductive state.
24. The method according to claim 17 , wherein the forming the porous layer comprises depositing a layer of a first semiconductor material, and then porosificating the first semiconductor material.
25. The method according to claim 24 , wherein the porosificating is carried out via electrochemical anodisation by using a base portion of the first electrode as an electrode for the electrochemical anodisation.
26. The method according to claim 24 , wherein a surface of a base portion of the first electrode is used as a barrier layer for the porosificating.
27. The method according to claim 24 , wherein the porosificating is stopped before it reaches a base portion of the first electrode, in order to preserve a layer of a non-porous semiconductor material under the porous layer.
28. The method according to claim 24 , wherein before the depositing the layer of the first semiconductor material, an underlying layer of a second semiconductor material different from the first semiconductor material, is deposited, the depositing the layer of the first semiconductor material is carried out in contact with the underlying layer, and a variation in electric potential is detected during an electrochemical anodisation corresponding to an end of oxidation of a thickness of the layer of the first semiconductor material and to a beginning of oxidation of the underlying layer, and the electrochemical anodisation is stopped upon detection of the variation in the electric potential.
29. The method according to claim 28 , wherein the first semiconductor material and the second semiconductor material are silicons having doping that differs by a type of dopant (p, n) or by a concentration of the same dopant.
30. The method according to claim 17 , further comprising thermal oxidation of at least a portion of a material of the porous layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 23, 2018
May 12, 2020
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