A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A power stage for a voltage regulator, the power stage comprising: one or more power transistor switches configured to output a phase current for the power stage; one or more power transistor gate drivers configured to turn the one or more power transistor switches off and on; a first pin configured to output temperature information for the power stage; a second pin configured to output current sense information for the power stage; and reporting circuitry configured to monitor and report information of the power stage, including: report temperature information for the power stage in a first nominal range at the first pin when no faults are detected, report phase current information for the power stage in a second nominal range at the second pin when no faults are detected, indicate to a controller that the power stage is switching under nominal conditions when the first pin is in the first nominal range and the second pin is in the second nominal range, indicate to the controller that the power stage is not switching under nominal conditions when the first pin is in an out-of-band range outside the first nominal range and/or the second pin is in an out-of-band range outside the second nominal range.
2. The power stage of claim 1 , wherein the reporting circuitry is configured to report a positive overcurrent condition in a first signalling band outside the second nominal range at the second pin and report a negative overcurrent condition in a second signalling band outside the second nominal range at the second pin, and wherein the first and the second signalling bands are nonoverlapping with each other.
3. The power stage of claim 1 , wherein the reporting circuitry is configured to report a supply under-voltage fault in a signalling band outside the first nominal range at the first pin.
4. The power stage of claim 1 , wherein the reporting circuitry is configured to report a supply under-voltage fault in a first signalling band outside the first nominal range at the first pin and in a second signalling band outside the second nominal range at the second pin.
5. The power stage of claim 1 , wherein the reporting circuitry is configured to report an overtemperature fault in a first signalling band outside the first nominal range at the first pin and in a second signalling band outside the second nominal range at the second pin.
6. The power stage of claim 1 , wherein the reporting circuitry is configured to report a phase fault in a first signalling band outside the first nominal range at the first pin and in a second signalling band outside the second nominal range at the second pin.
7. The power stage of claim 1 , wherein the reporting circuitry is configured to report a boot supply under-voltage fault in a first signalling band outside the first nominal range at the first pin and in a second signalling band outside the second nominal range at the second pin.
8. The power stage of claim 1 , wherein the reporting circuitry is configured to: report a positive overcurrent condition in a first signalling band outside the second nominal range at the second pin; report a negative overcurrent condition in a second signalling band outside the second nominal range at the second pin, the first and the second signalling bands being nonoverlapping with each other; report a supply under-voltage fault in a third signalling band outside the first nominal range at the first pin, or in the third signalling band at the first pin and in the second signalling band at the second pin; report an overtemperature fault in a fourth signalling band outside the first nominal range at the first pin and in the second signalling band at the second pin, the third and the fourth signalling bands being nonoverlapping with each other; report a phase fault in the fourth signalling band at the first pin and in the first signalling band at the second pin; and report a boot supply under-voltage fault in the third signalling band at the first pin and in the first signalling band at the second pin.
9. The power stage of claim 1 , wherein the reporting circuitry is configured to indicate to the controller that the power stage is truncating PWM pulses provided by the controller for switching the one or more power transistor switches, when the first pin is in an out-of-band range outside the first nominal range and/or the second pin is in an out-of-band range outside the second nominal range.
10. The power stage of claim 1 , wherein the power stage is configured to enter a sleep mode when the first pin is in an out-of-band range outside the first nominal range and/or the second pin is in an out-of-band range outside the second nominal range.
11. A controller for a voltage regulator, the controller comprising: a first pin configured to receive aggregate temperature information from a plurality of power stages coupled to the first pin, the aggregate temperature information indicating the highest temperature reported by all of the power stages; a plurality of second pins, each second pin configured to receive phase current information from one of the power stages; and control circuitry configured to control operation of the power stages, determine that the power stages are switching under nominal conditions when the first pin is in a first nominal range and each second pin is in a second nominal range, and modify the control of one or more of the power stages responsive to determining that one or more of the power stages is not switching under nominal conditions when the first pin is in an out-of-band range outside the first nominal range and/or one or more of the second pins is in an out-of-band range outside the second nominal range.
12. The controller of claim 11 , wherein the control circuitry is configured to track power stage faults and corresponding fault types over time, to identify predominant failure mechanisms.
13. The controller of claim 12 , wherein the control circuitry is configured to track the state of the first pin and the plurality of second pins over time to determine whether a power stage fault was cleared when the power stage that reported the fault entered sleep mode, and to determine the corresponding fault type based on the tracked state of the first pin and the plurality of second pins.
14. The controller of claim 11 , wherein the control circuitry is configured to determine that one or more of the power stages is in a start-up mode based on the first pin being in an out-of-band range outside the first nominal range and/or one or more of the second pins being in an out-of-band range outside the second nominal range.
15. The controller of claim 11 , wherein the control circuitry is configured to determine that one or more of the power stages is in a low power mode based on the first pin being in an out-of-band range outside the first nominal range and/or one or more of the second pins being in an out-of-band range outside the second nominal range.
16. The controller of claim 11 , wherein the control circuitry is configured to determine that one or more of the power stages cleared a fault type by entering and exiting a low power mode based on the first pin being in an out-of-band range outside the first nominal range and/or one or more of the second pins being in an out-of-band range outside the second nominal range.
17. A voltage regulator system, comprising: a controller; and a plurality of power stages, each power stage comprising: one or more power transistor switches configured to output a phase current for the power stage; one or more power transistor gate drivers configured to turn the one or more power transistor switches off and on; a first pin configured to output temperature information for the power stage; a second pin configured to output current sense information for the power stage; and reporting circuitry configured to monitor and report information of the power stage, including: report temperature information for the power stage in a first nominal range at the first pin when no faults are detected, report phase current information for the power stage in a second nominal range at the second pin when no faults are detected, indicate to the controller that the power stage is switching under nominal conditions when the first pin is in the first nominal range and the second pin is in the second nominal range, indicate to the controller that the power stage is not switching under nominal conditions when the first pin is in an out-of-band range outside the first nominal range and/or the second pin is in an out-of-band range outside the second nominal range wherein the controller comprises: a first pin coupled to the first pin of each power stage; a plurality of second pins, each second pin of the controller coupled to the second pin of one of the power stages; control circuitry configured to control operation of the power stages, determine that the power stages are switching under nominal conditions when the first pin is in a first nominal range and each second pin is in a second nominal range, and modify the control of one or more of the power stages responsive to determining that one or more of the power stages is not switching under nominal conditions when the first pin is in an out-of-band range outside the first nominal range and/or one or more of the second pins is in an out-of-band range outside the second nominal range.
18. The voltage regulator system of claim 17 , wherein the control circuitry of the controller is configured to track power stage faults and corresponding fault types over time, to identify predominant failure mechanisms.
19. The voltage regulator system of claim 18 , wherein the control circuitry of the controller is configured to track the state of the first pin and the plurality of second pins of the controller over time to determine whether a power stage fault was cleared when the power stage that reported the fault entered sleep mode, and to determine the corresponding fault type based on the tracked state of the first pin and the plurality of second pins of the controller.
20. The voltage regulator system of claim 17 , wherein the control circuitry of the controller is configured to determine that one or more of the power stages is in a start-up mode based on the first pin of the controller being in an out-of-band range outside the first nominal range and/or one or more of the second pins of the controller being in an out-of-band range outside the second nominal range.
21. The voltage regulator system of claim 17 , wherein the control circuitry of the controller is configured to determine that one or more of the power stages is in a low power mode based on the first pin of the controller being in an out-of-band range outside the first nominal range and/or one or more of the second pins of the controller being in an out-of-band range outside the second nominal range.
22. The voltage regulator system of claim 17 , wherein the control circuitry of the controller is configured to determine that one or more of the power stages cleared a fault type by entering and exiting a low power mode based on the first pin of the controller being in an out-of-band range outside the first nominal range and/or one or more of the second pins of the controller being in an out-of-band range outside the second nominal range.
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December 28, 2018
May 19, 2020
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