A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of designing a semiconductor device, the method comprising: placing a first cell adjacent to a second cell into a first cell row; placing a third cell adjacent to a fourth cell into a second cell row adjacent to the first cell row, wherein a region at an intersection of the first cell, the second cell, the third cell, and the fourth cell comprises: a first drain region of the first cell; a first source region of the second cell; a second source region of the third cell; and a second drain region of the fourth cell; performing a post placement treatment after the placing the first cell and the second cell and after the placing the third cell and the fourth cell, wherein the post placement treatment comprises: combining a first via in the first cell and a second via in the third cell into a third via; and removing a fourth via from the first cell; and manufacturing a semiconductor device with the third via with a semiconductor device manufacturing tool.
2. The method of claim 1 , wherein prior to the removing the fourth via the fourth via connects a cell boundary conductor with a ground rail.
3. The method of claim 2 , wherein the cell boundary conductor remains electrically connected to the ground rail through a metal zero connection.
4. The method of claim 1 , wherein the first cell is an inverter.
5. The method of claim 4 , wherein the second cell is an inverter.
6. The method of claim 5 , wherein the third cell is an inverter and the fourth cell is an inverter.
7. A method of manufacturing a semiconductor device, the method comprising: choosing a first cell and a second cell from a cell library; placing the first cell and the second cell adjacent to each other; placing a first marker layer around a first via within the first cell and a second via in the second cell; determining, based at least in part on a location of the first marker layer, whether to merge the first via and the second via into a third via; and manufacturing the third via with a semiconductor manufacturing processing machine, wherein the determining whether to merge the first via and the second via comprises expanding the second via in a first direction perpendicular to a first cell row to form a first expansion zone, the first cell row comprising the first cell and the second cell, and wherein the determining whether to merge the first via and the second via comprises expanding a third via in a second direction perpendicular with the first cell row and different from the first direction to form a second expansion zone.
8. The method of claim 7 , wherein the manufacturing the third via manufactures the third via in electrical connection with a first metal zero connection that is in physical contact with a first source/drain region.
9. The method of claim 8 , wherein the first metal zero connection has a first portion in physical contact with a first cell boundary conductor in the second cell.
10. The method of claim 7 , wherein the first cell is a first inverter.
11. The method of claim 10 , wherein the second cell is a second inverter.
12. The method of claim 11 , wherein the third cell is a third inverter.
13. The method of claim 12 , wherein the fourth cell is a fourth inverter.
14. The method of claim 7 , further comprising merging the first via and the second via when the first expansion zone contacts the second expansion zone.
15. The method of claim 7 , wherein a region at an intersection of the first cell and the second cell comprises a first drain region of the first cell and a first source region of the second cell.
16. A semiconductor device comprising: a first cell row with a first cell and a second cell adjacent to the first cell; a second cell row adjacent to the first cell row, wherein the second cell row comprises a third cell and a fourth cell, wherein a region at an intersection of the first cell, the second cell, the third cell, and the fourth cell comprises: a first source region of the first cell; a first drain region of the second cell; a second drain region of the third cell; and a third drain region of the fourth cell, wherein a first via and a second via are combined into an “L” shape; and a via electrically connecting a power/ground rail to a first source/drain region and a second source/drain region, the first source/drain region being located in the second cell and the second source/drain region being located in the fourth cell, the via extending into both the second cell and the fourth cell.
17. The semiconductor device of claim 16 , wherein the via is electrically connected to a first metal zero connection that is in physical contact with the first source/drain region.
18. The semiconductor device of claim 17 , wherein the first metal zero connection has a first portion in physical contact with a first cell boundary conductor in the second cell.
19. The semiconductor device of claim 18 , wherein the first metal zero connection has a second portion in physical contact with a contact in the fourth cell.
20. The semiconductor device of claim 16 , wherein the first cell is a first inverter, the second cell is a second inverter, the third cell is a third inverter, and the fourth cell is a fourth inverter.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 4, 2018
May 26, 2020
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