A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a first clocked inverter electrically connected to a first node wherein first data are input to the first node, the first clocked inverter being configured to respond to a first transition of a reference clock; a second clocked inverter electrically connected to a second node wherein second data are input to the second node, the second clocked inverter being configured to respond to a second transition of the reference clock, the second transition being an opposite transition than the first transition; a first inverter electrically connected to the first node; a second inverter electrically connected to the second node; a third clocked inverter electrically connected to an output node of the first inverter, and configured to respond to the first transition of the reference clock; a fourth clocked inverter electrically connected to an output node of the second inverter, and configured to respond to the second transition of the reference clock; a third inverter electrically connected to an output node of the first clocked inverter and an output node of the second clocked inverter; a fourth inverter electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter; and a comparison circuit electrically connected to an output node of the third inverter and an output node of the fourth inverter.
2. The semiconductor device according to claim 1 , further comprising: a first latch circuit configured to supply the first data to the first node; and a second latch circuit configured to supply the second data to the second node.
3. The semiconductor device according to claim 1 , wherein the comparison circuit includes a comparator having a non-inverting input terminal electrically connected to the output node of the third inverter and an inverting input terminal electrically connected to the output node of the fourth inverter.
4. The semiconductor device according to claim 3 , wherein the comparator includes a differential amplifier.
5. The semiconductor device according to claim 1 , wherein the comparison circuit includes: a fifth inverter electrically connected to the output node of the third inverter; a sixth inverter electrically connected to the output node of the fourth inverter; a seventh inverter electrically inserted between a first line located at an output side of the fifth inverter and a second line located at an output side of the sixth inverter in a first polarity; and an eighth inverter electrically inserted between the first line and the second line in a second polarity reverse to the first polarity.
6. The semiconductor device according to claim 5 , wherein the comparison circuit further includes: a ninth inverter electrically connected to the first line; a tenth inverter electrically connected to the second line; an eleventh inverter electrically inserted between a third line located at an output side of the ninth inverter and a fourth line located at an output side of the tenth inverter in the first polarity; and a twelfth inverter electrically inserted between the third line and the fourth line in the second polarity.
7. The semiconductor device according to claim 1 , wherein the comparison circuit includes: a fifth inverter electrically inserted between a first line located at an output side of the third inverter and a second line located at an output side of the fourth inverter in a first polarity; and a sixth inverter electrically inserted between the first line and the second line in a second polarity reverse to the first polarity.
8. The semiconductor device according to claim 1 , further comprising a generation circuit configured to generate a first clock obtained by inverting the reference clock and a second clock obtained by not inverting the reference clock, wherein the first clocked inverter has a clock node at a first side which receives the first clock and a clock node at a second side which receives the second clock, wherein the second clocked inverter has a clock node at the first side which receives the second clock and a clock node at the second side which receives the first clock, wherein the third clocked inverter has a clock node at the first side which receives the first clock and a clock node at the second side which receives the second clock, and wherein the fourth clocked inverter has a clock node at the first side which receives the second clock and a clock node at the second side which receives the first clock.
9. The semiconductor device according to claim 8 , wherein the generation circuit includes a first chain circuit configured to provide the first clock, and a second chain circuit configured to provide the second clock.
10. The semiconductor device according to claim 9 , wherein each of the first chain circuit and the second chain circuit include a plurality of inverters connected sequentially in series, respectively.
11. A memory system comprising: a semiconductor memory; and a controller including an interface circuit that includes a semiconductor device, and configured to control the semiconductor memory, the semiconductor device comprising: a first clocked inverter electrically connected to a first node wherein first data are input to the first node, the first clocked inverter being configured to respond to a first transition of a reference clock, a second clocked inverter electrically connected to a second node wherein second data are input to the second node, the second clocked inverter being configured to respond to a second transition of the reference clock; the second transition being an opposite transition than the first transition; a first inverter electrically connected to the first node; a second inverter electrically connected to the second node; a third clocked inverter electrically connected to an output node of the first inverter, and configured to respond to the first transition of the reference clock; a fourth clocked inverter electrically connected to an output node of the second inverter, and configured to respond to the second transition of the reference clock; a third inverter electrically connected to an output node of the first clocked inverter and an output node of the second clocked inverter; a fourth inverter electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter; and a comparison circuit electrically connected to an output node of the third inverter and an output node of the fourth inverter.
12. The memory system according to claim 11 , the semiconductor device further comprising: a first latch circuit configured to supply the first data to the first node; and a second latch circuit configured to supply the second data to the second node.
13. The memory system according to claim 11 , wherein the comparison circuit includes a comparator having a non-inverting input terminal electrically connected to the output node of the third inverter and an inverting input terminal electrically connected to the output node of the fourth inverter.
14. The memory system according to claim 13 , wherein the comparator includes a differential amplifier.
15. The memory system according to claim 11 , wherein the comparison circuit includes: a fifth inverter electrically connected to the output node of the third inverter; a sixth inverter electrically connected to the output node of the fourth inverter; a seventh inverter electrically inserted between a first line located at an output side of the fifth inverter and a second line located at an output side of the sixth inverter in a first polarity; and an eighth inverter electrically inserted between the first line and the second line in a second polarity reverse to the first polarity.
16. The memory system according to claim 15 , wherein the comparison circuit further includes: a ninth inverter electrically connected to the first line; a tenth inverter electrically connected to the second line; an eleventh inverter electrically inserted between a third line located at an output side of the ninth inverter and a fourth line located at an output side of the tenth inverter in the first polarity; and a twelfth inverter electrically inserted between the third line and the fourth line in the second polarity.
17. The memory system according to claim 11 , wherein the comparison circuit includes: a fifth inverter electrically inserted between a first line located at an output side of the third inverter and a second line located at an output side of the fourth inverter in a first polarity; and a sixth inverter electrically inserted between the first line and the second line in a second polarity reverse to the first polarity.
18. The memory system according to claim 11 , the semiconductor device further comprising a generation circuit configured to generate a first clock obtained by inverting the reference clock and a second clock obtained by not inverting the reference clock, wherein the first clocked inverter has a clock node at a first side which receives the first clock and a clock node at a second side which receives the second clock, wherein the second clocked inverter has a clock node at the first side which receives the second clock and a clock node at the second side which receives the first clock, wherein the third clocked inverter has a clock node at the first side which receives the first clock and a clock node at the second side which receives the second clock, and wherein the fourth clocked inverter has a clock node at the first side which receives the second clock and a clock node at the second side which receives the first clock.
19. The memory system according to claim 18 , wherein the generation circuit includes a first chain circuit configured to provide the first clock, and a second chain circuit configured to provide the second clock.
20. The memory system according to claim 19 , wherein each of the first chain circuit and the second chain circuit include a plurality of inverters connected sequentially in series, respectively.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 29, 2018
May 26, 2020
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