Systems and methods using a three-dimensional memory device with a number of memory cells disposed vertically in a number of pillars arranged along a horizontal direction can be used in a variety of applications. In various embodiments, pillars of memory cells may be disposed between lower and upper digitlines respectively coupled to different sense amplifiers to provide read/write operations and refresh operations. In various embodiments, a three-dimensional memory device having an array of memory cells vertically arranged in pillars may include a sense amplifier and digitline with a static random access memory cache, where the static random access memory cache is disposed below the array of memory cells in the same die. Additional apparatus, systems, and methods are disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device comprising: an array of memory cells, the array being a three-dimensional array of pillars with each pillar having memory cells stacked vertically in the pillar, a number of the pillars arranged along a horizontal direction; a first digitline disposed below the array, the first digitline coupled to each pillar of the pillars along the horizontal direction by a respective first select device; a second digitline above the array, the second digitline coupled to each pillar of the pillars along the horizontal direction by a respective second select device; a first sense amplifier coupled to the first digitline; a second sense amplifier coupled to the second digitline; and an input/output circuit coupled to the first sense amplifier or the second sense amplifier.
2. The memory device of claim 1 , wherein the memory device includes control circuitry to access a first memory cell in one pillar of the pillars along the horizontal direction via an access line coupled to the first memory cell and via one of the first digitline or the second digitline coupled to the one pillar and to access a second memory cell in another pillar of the pillars along the horizontal direction via an access line coupled to the second memory cell and via the other one of the first digitline or the second digitline.
3. The memory device of claim 2 , wherein the control circuitry is operable to control the access to the first memory cell and the access to the second memory cell in time intervals that overlap.
4. The memory device of claim 1 , wherein each of the memory cells in each pillar is a dynamic random access memory cell coupled to a pillar digitline of the respective pillar, the pillar digitline coupled to the respective first select device to the respective second select device of the respective pillar.
5. The memory device of claim 1 , wherein the memory device includes a static random access memory structured to store a bit from a memory cell of each of a selected number of pillars of the pillars along the horizontal direction, the static random access memory integrated in a die with the array of memory cells.
6. The memory device of claim 5 , wherein the static random access memory is structured below the array of memory cells.
7. The memory device of claim 6 , wherein the memory device includes a processor disposed in the die below the array of memory cells to control the static random access memory.
8. The memory device of claim 1 , wherein the memory device includes a second input/output circuit coupled to the first sense amplifier or the second sense amplifier not coupled to the input/output circuit.
9. A memory device comprising: an array of memory cells in a die, the array being a three-dimensional array of pillars with each pillar having memory cells stacked vertically in the pillar, a number of the pillars arranged along a horizontal direction; a digitline disposed below the array or above the array, the digitline coupled to each pillar of the pillars along the horizontal direction by a respective select device coupled to a pillar digitline of the respective pillar; a static random access memory cache integrated in the die with the array of memory cells and disposed below the array of memory cells; a sense amplifier coupled to the digitline; and an input/output circuit coupled to the sense amplifier.
10. The memory device of claim 9 , wherein the memory device is arranged to read data from the array into the static random access memory cache and to write the data back to the array.
11. The memory device of claim 10 , wherein the memory device is operable at rates to read the data from the array into the static random access memory cache at approximately 10 petabps and write the data back to the array in an interval from about 5 petabps to about 10 petabps.
12. The memory device of claim 9 , wherein the array and the static random access memory cache share the digitline and the sense amplifier.
13. The memory device of claim 9 , wherein the memory device includes a processor disposed in the die below the array of memory cells to control the static random access memory.
14. A method comprising: writing or reading data to or from a memory cell of an array of memory cells using a first digitline coupled to a first sense amplifier, the array being a three-dimensional array of pillars with each pillar having memory cells stacked vertically in the respective pillar, a number of the pillars arranged along a horizontal direction; and refreshing a memory cell, in a pillar different from a pillar containing the memory cell to which the data is written or read, using a second digitline coupled to a second sense amplifier, wherein one of the first digitline and the second digitline is disposed below the array and the other of the first digitline and the second digitline is disposed above the array.
15. The method of claim 14 , wherein the method includes continuously refreshing memory cells in pillars different from a pillar in which data is being read from or written to a memory cell.
16. The method of claim 14 , wherein writing or reading data includes reading one or more bits from one or more pillars of the array into a static random access memory disposed below the array of memory cells.
17. The method of claim 14 , wherein the method includes storing a new cache page into a static random access memory cache disposed below the array of memory cells and, before loading the new page into the static random access memory cache, storing back to the array an existing page stored in the static random access memory cache.
18. A method comprising: writing or reading data into a static random access memory cache integrated in a die of a memory device with an array of memory cells and disposed below the array of memory cells, the array being a three-dimensional array of pillars with each pillar having memory cells stacked vertically in the pillar, a number of the pillars arranged along a horizontal direction, wherein the static random access memory cache and the array share a digitline and a sense amplifier coupled to the digitline to conduct storage operations.
19. The method of claim 18 , wherein the method includes porting out the data from the static random access memory cache through the sense amplifier to input/output circuitry to transmit the data out of the memory device.
20. The method of claim 18 , wherein the method includes storing a new cache page into the static random access memory cache and, before loading the new page into the static random access memory cache, storing hack to the array an existing page stored in the static random access memory cache.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 22, 2019
June 2, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.