A shift register, an array substrate and a display device in the field of display technology are provided in the present disclosure. In the shift register, the gate electrode of the first transistor is connected to a second node, one of the source electrode and the drain electrode is connected to a first clock signal line, and the other one is connected to the first node. The gate electrode of the second transistor is connected to the second node, one of the source electrode and the drain electrode is connected to the second node, and the other one is connected to the first clock signal line. The charging circuitry is configured to set the second node to an effective level when a second clock signal line is at an effective level. The memory circuitry is configured to store the threshold voltage of the second transistor and compensate the threshold voltage of the first transistor with the stored threshold voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A shift register, comprising: a first transistor, wherein one of a source electrode and a drain electrode of the first transistor is connected to a first clock signal line, and the other one is connected to a first node, and a gate electrode of the first transistor is connected to a second node; a second transistor, wherein a gate electrode of the second transistor is connected to the second node, one of a source electrode and a drain electrode of the second transistor is connected to the second node, and the other one is connected to the first clock signal line; a charging circuitry connected to the second node and a second clock signal line and configured to set the second node to an effective level when the second clock signal line is at an effective level; a memory circuitry connected to the second node and the first clock signal line and configured to store a threshold voltage of the second transistor and to compensate a threshold voltage of the first transistor with the stored threshold voltage; wherein, the first transistor and the second transistor have the same threshold voltage.
2. The shift register according to claim 1 , wherein the memory circuitry is configured to store the threshold voltage of the second transistor when the second node discharges the first clock signal line through the second transistor; and to compensate the threshold voltage of the first transistor with the stored threshold voltage when the first clock signal line changes a level at the first node through the first transistor.
3. The shift register according to claim 1 , wherein during the same clock inversion process, a moment when an effective level is changed to an ineffective level on the second clock signal line is earlier than a moment when an ineffective level is changed to an effective level on the first clock signal line.
4. The shift register according to claim 1 , wherein the memory circuitry comprises a first capacitor, wherein a first terminal of the first capacitor is connected to the second node, and a second terminal of the first capacitor is connected to the first clock signal line.
5. The shift register according to claim 1 , wherein the charging circuitry comprises a third transistor, wherein a gate electrode of the third transistor is connected to the second clock signal line, one of a source electrode and a drain electrode of the third transistor is connected to the second clock signal line, and the other one is connected to the second node.
6. The shift register according to claim 1 , further comprising an output terminal, and a third node configured to control signal output; and the shift register further comprising: a fourth transistor, wherein a gate electrode of the fourth transistor is connected to the third node, one of a source electrode and a drain electrode of the fourth transistor is connected to the second clock signal line, and the other one is connected to the output terminal.
7. The shift register according to claim 1 , further comprising an output terminal and a third node configured to control signal output; and the shift register further comprising: a tenth transistor, wherein a gate electrode of the tenth transistor is connected to the first node, one of the source electrode and the drain electrode of the tenth transistor is connected to the third first node, and the other one is connected to an ineffective-level voltage line; an eleventh transistor, wherein a gate electrode of the eleventh transistor is connected to the first node, one of a source electrode and a drain electrode of the eleventh transistor is connected to the output terminal, and the other one is connected to the ineffective-level voltage line; and a twelfth transistor, wherein a gate electrode of the twelfth transistor is connected to the third node, one of a source electrode and a drain electrode of the twelfth transistor is connected to the first node, and the other one is connected to the ineffective-level voltage line.
8. The shift register according to claim 6 , further comprising: a second capacitor, wherein a first terminal of the second capacitor is connected to the third node, and a second terminal of the second capacitor is connected to the output terminal.
9. The shift register according to claim 8 , further comprising an input terminal, and a reset terminal; and the shift register further comprising: a fifth transistor, wherein a gate electrode of the fifth transistor is connected to the input terminal, one of a source electrode and a drain electrode of the fifth transistor is connected to the input terminal, and the other one is connected to the third node; a sixth transistor, wherein a gate electrode of the sixth transistor is connected to the reset terminal, one of a source electrode and a drain electrode of the sixth transistor is connected to the third node, and the other one is connected to an ineffective-level voltage line; and a seventh transistor, wherein a gate electrode of the seventh transistor is connected to the reset terminal, one of a source electrode and a drain electrode of the seventh transistor is connected to the output terminal, and the other one is connected to the ineffective-level voltage line.
10. The shift register according to claim 9 , further comprising: an eighth transistor, wherein a gate electrode of the eighth transistor is connected to the first clock signal line, one of a source electrode and a drain electrode of the eighth transistor is connected to the input terminal, and the other one is connected to the third node.
11. The shift register according to claim 10 , further comprising: a ninth transistor, wherein a gate electrode of the ninth transistor is connected to the first clock signal line, one of a source electrode and a drain electrode of the ninth transistor is connected to the output terminal, and the other one is connected to the ineffective-level voltage line.
12. The shift register according to claim 11 , further comprising: a tenth transistor, wherein a gate electrode of the tenth transistor is connected to the first node, one of the source electrode and the drain electrode of the tenth transistor is connected to the third node, and the other one is connected to the ineffective-level voltage line; an eleventh transistor, wherein a gate electrode of the eleventh transistor is connected to the first node, one of a source electrode and a drain electrode of the eleventh transistor is connected to the output terminal, and the other one is connected to the ineffective-level voltage line; and a twelfth transistor, wherein a gate electrode of the twelfth transistor is connected to the third node, one of a source electrode and a drain electrode of the twelfth transistor is connected to the first node, and the other one is connected to the ineffective-level voltage line.
13. The shift register according to claim 1 , wherein the first clock signal line and the second clock signal line are each loaded with one of a positive-phase clock signal and an inverted-phase clock signal respectively.
14. An array substrate, comprising a shift register, wherein the shift register comprises: a first node configured to control signal resetting; a first transistor, wherein a gate electrode of the first transistor is connected to a second node, one of a source electrode and a drain electrode of the first transistor is connected to a first clock signal line, and the other one is connected to the first node; a second transistor, wherein a gate electrode of the second transistor is connected to the second node, one of a source electrode and a drain electrode of the second transistor is connected to the second node, and the other one is connected to the first clock signal line; a charging circuitry connected to the second node and a second clock signal line and configured to set the second node to an effective level when the second clock signal line is at an effective level; a memory circuitry connected to the second node and the first clock signal line and configured to store a threshold voltage of the second transistor, and to compensate a threshold voltage of the first transistor with the stored threshold voltage; wherein, the first transistor and the second transistor have the same threshold voltage.
15. A display device, comprising the array substrate according to claim 14 .
16. The array substrate according to claim 14 , wherein the memory circuitry is configured to store the threshold voltage of the second transistor when the second node discharges the first clock signal line through the second transistor; and to compensate the threshold voltage of the first transistor with the stored threshold voltage when the first clock signal line changes a level at the first node through the first transistor.
17. The array substrate according to claim 14 , wherein during the same clock inversion process, a moment when an effective level is changed to an ineffective level on the second clock signal line is earlier than a moment when an ineffective level is changed to an effective level on the first clock signal line.
18. The array substrate according to claim 14 , wherein the memory circuitry comprises a first capacitor, wherein a first terminal of the first capacitor is connected to the second node, and a second terminal of the first capacitor is connected to the first clock signal line.
19. The array substrate according to claim 14 , wherein the charging circuitry comprises a third transistor, wherein a gate electrode of the third transistor is connected to the second clock signal line, one of a source electrode and a drain electrode of the third transistor is connected to the second clock signal line, and the other one is connected to the second node.
20. The array substrate according to claim 14 , wherein the first clock signal line and the second clock signal line are each loaded with one of a positive-phase clock signal and an inverted-phase clock signal respectively.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 3, 2017
June 2, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.