A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A foundry-agnostic post-processing method, comprising: removing a wafer from an output yield at a foundry, the wafer comprising an intermediate layer with a via between an active surface and a substrate; removing other wafers similar to the wafer from output yields of other foundries; and compiling the wafer and the other wafers into a wafer set in a post-processing facility, wherein, for each wafer and other wafer of the wafer set, the method further comprises: thinning the substrate to the intermediate layer at locations remote from the via to expose a new surface; avoiding the thinning at a location of the via to form a bump; and bonding the new surface to an alternate material substrate while absorbing the bump such that the alternate material substrate is flat at a location corresponding to the location of the via.
2. The foundry-agnostic post-processing method according to claim 1 , wherein at least one of the active surface and the substrate comprises at least one of silicon (Si) and silicon germanium (SiGe) and wherein the alternate material substrate comprises a high resistivity material.
3. The foundry-agnostic post-processing method according to claim 1 , wherein the alternate material substrate comprises at least one of glass and fused silica.
4. The foundry-agnostic post-processing method according to claim 1 , wherein the bonding comprises oxide bonding.
5. The foundry-agnostic post-processing method according to claim 1 , wherein the thinning comprises: grinding of outer layers of the substrate; and chemical mechanical polishing of inner layers of the substrate.
6. The foundry-agnostic post-processing method according to claim 1 , wherein the thinning comprises: recognizing existence of a via in the wafer; and avoiding an execution of the thinning at a location of the via.
7. The foundry-agnostic post-processing method according to claim 1 , further comprising: obtaining similar wafers from a plurality of foundries; executing one or more of the removing, thinning and bonding to each of the similar wafers; and optimizing executions of the one or more of the removing, thinning and bonding for each of the similar wafers.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 3, 2019
June 9, 2020
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