A thin film transistor includes a substrate, a gate electrode disposed on the substrate, an active pattern disposed on the gate electrode, a source electrode electrically coupled to the active pattern and a drain electrode electrically coupled to the active pattern. The active pattern includes a first channel layer overlapping the source electrode and the drain electrode and a second channel layer overlapping the gate electrode. The second channel layer includes a plurality of high electron mobility regions. An electron mobility of each of the high electron mobility regions is greater than an electron mobility of the first channel layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A thin film transistor, comprising: a substrate; a gate electrode disposed on the substrate; a gate insulation layer disposed on the gate electrode; an active pattern disposed on the gate insulation layer; a source electrode electrically coupled to the active pattern; and a drain electrode electrically coupled to the active pattern, wherein the active pattern comprises: a first channel layer overlapping the source electrode and the drain electrode; and a second channel layer overlapping the gate electrode, wherein the second channel layer comprises at least three high electron mobility regions and amorphous silicon, the amorphous silicon being directly disposed on the gate insulation layer and each of the high electron mobility regions contacting the amorphous silicon without contacting the gate insulation layer, wherein an electron mobility of each of the high electron mobility regions is greater than an electron mobility of the first channel layer, and wherein each of the high electron mobility regions includes polysilicon.
2. The thin film transistor of claim 1 , wherein the high electron mobility regions are spaced apart from each other.
3. The thin film transistor of claim 1 , wherein a diameter of each of the high electron mobility regions is within a range of about 1 nm to about 10 nm.
4. The thin film transistor of claim 1 , wherein a hydrogen content of each of the high electron mobility regions is greater than a hydrogen content of the first channel layer.
5. The thin film transistor of claim 1 , wherein a top surface and a side surface of the second channel layer are covered by the first channel layer.
6. The thin film transistor of claim 1 , wherein the active pattern is disposed between the source/drain electrode and the gate electrode.
7. The thin film transistor of claim 1 , wherein the high electron mobility regions overlap the gate electrode.
8. A liquid crystal display apparatus, comprising: a first substrate comprising a gate electrode, a gate insulation layer disposed on the gate electrode, an active pattern disposed on the gate insulation layer, a source electrode electrically coupled to the active pattern, a drain electrode electrically coupled to the active pattern and a pixel electrode electrically coupled to the drain electrode; a second substrate opposite to the first substrate; and a liquid crystal layer disposed between the first and second substrates, wherein the active pattern comprises: a first channel layer disposed between each of the source electrode, the drain electrode and the gate electrode; and a second channel layer disposed between the gate electrode and the first channel layer, wherein the second channel layer comprises at least three high electron mobility regions and amorphous silicon, the amorphous silicon being directly disposed on the gate insulation layer and each of the high electron mobility regions contacting the amorphous silicon without contacting the gate insulation layer, wherein an electron mobility of each of the high electron mobility regions is greater than an electron mobility of the first channel layer, and wherein each of the high electron mobility regions includes polysilicon.
9. The liquid crystal display apparatus of claim 8 , wherein the high electron mobility regions are spaced apart from each other.
10. The liquid crystal display apparatus of claim 8 , wherein a diameter of each of the high electron mobility regions is within a range of about 1 nm to about 10 nm.
11. The liquid crystal display apparatus of claim 8 , wherein a hydrogen content of each of the high electron mobility regions is greater than a hydrogen content of the first channel layer.
12. The liquid crystal display apparatus of claim 8 , wherein a top surface and a side surface of the second channel layer are covered by the first channel layer and an insulation layer respectively.
13. The liquid crystal display apparatus of claim 8 , wherein the active pattern is disposed between the source/drain electrode and the gate electrode.
14. A method of manufacturing a thin film transistor, comprising: forming a gate electrode on a substrate; forming a gate insulation layer on the gate electrode; sequentially forming an active layer and a data metal layer on the gate insulation layer; forming a first photoresist pattern on the data metal layer; patterning the data metal layer into a data metal pattern and patterning the active layer into a preliminary active pattern using the first photoresist pattern as an etch stop layer; forming a second photoresist pattern by partially removing the first photoresist pattern, forming a source electrode and a drain electrode by patterning the data metal pattern using the second photoresist pattern as an etch stop layer; and forming an active pattern by performing a hydrogen ion beam implantation process and an annealing process at the preliminary active pattern, wherein the active pattern includes a first channel layer and a second channel layer, wherein the second channel layer includes at least three high electron mobility regions and amorphous silicon, the amorphous silicon being directly disposed on the gate insulation layer and each of the high electron mobility regions contacting the amorphous silicon without contacting the gate insulation layer, wherein an electron mobility of each of the high electron mobility regions is greater than an electron mobility of the first channel layer, and wherein each of the high electron mobility regions includes polysilicon.
15. The method of manufacturing a thin film transistor of claim 14 , wherein performing the hydrogen ion beam implantation process further comprises: accelerating a hydrogen ion beam within a range of about 10 keV to about 30 key; and implanting the hydrogen ion beam at the preliminary active pattern.
16. The method of manufacturing a thin film transistor of claim 14 , wherein performing the annealing process further comprises: annealing the preliminary active pattern within a range of about 250 degree Celsius to about 300 degree Celsius.
17. The method of manufacturing a thin film transistor of claim 14 , further comprising: forming an insulation layer covering the preliminary active pattern, the source electrode and the drain electrode.
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March 15, 2016
June 9, 2020
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