A disclosed DFE selection element reduces the degree of unrolling that might otherwise be required. In one illustrative embodiment of a method for converting a receive signal from a communication channel into a sequence of symbol decisions, the method includes, for each sampling interval: (a) generating a set of tentative symbol decisions each having a thermometer-coded representation with a least significant bit and a most significant bit; (b) providing each least significant bit as a thermometer-coded input to a first multiplexer; (c) providing each most significant bit as a thermometer-coded input to a second multiplexer; (d) applying a thermometer-coded representation of a preceding output symbol decision as selection inputs to the first and second multiplexers; and (e) capturing a current output symbol decision having a thermometer-coded representation that includes outputs of the first and second multiplexer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of converting a receive signal from a communication channel into a sequence of symbol decisions, the method comprising, for each sampling interval: generating, via a precompensation unit, a set of tentative symbol decisions each having a thermometer-coded representation with a least significant bit and a most significant bit; providing each least significant bit as a thermometer-coded input to a first multiplexer; providing each most significant bit as a thermometer-coded input to a second multiplexer; applying a thermometer-coded representation of a preceding output symbol decision as selection inputs to the first and second multiplexers; and capturing a current output symbol decision having a thermometer-coded representation that includes outputs of the first and second multiplexer.
2. The method of claim 1 , wherein each of the first and second multiplexers consists of parallel circuit paths between an output node and a common node, each path having at most one selection bit controlled transistor in series with at most one input bit controlled transistor.
3. The method of claim 2 , wherein one of the parallel circuit paths has a least significant selection bit controlling a transistor in series with a transistor controlled by a least significant input bit.
4. The method of claim 2 , wherein one of the parallel circuit paths has a most significant selection bit controlling a transistor in series with a transistor controlled by a most significant input bit.
5. The method of claim 1 , wherein the tentative symbol decisions, the preceding output symbol decision, and the current output symbol decision, each have a thermometer-coded representation with one or more bits of intermediate significance.
6. The method of claim 1 , wherein said generating includes: processing the receive signal with a front end filter to produce a filtered signal having reduced leading intersymbol interference.
7. The method of claim 6 , wherein said generating further includes: deriving a feedback signal from past output symbol decisions; subtracting the feedback signal from the filtered signal to obtain a combined signal having reduced trailing intersymbol interference; and operating on the combined signal with a precompensation unit to provide each set of tentative symbol decisions.
8. The method of claim 1 , wherein the tentative symbol decisions are chosen from a pulse amplitude modulation (PAM) constellation having at least four symbol values.
9. A channel interface module that comprises a receiver having: a precompensation unit that produces at each of multiple time intervals a set of tentative symbol decisions each having a multibit thermometer-coded representation, each tentative symbol decision accounting for trailing intersymbol interference from a speculative preceding symbol value; and a recursive selection unit that includes bitwise multiplexers to select from each set a current symbol decision based on a preceding symbol decision, the current and preceding symbol decisions each having a multibit thermometer-coded representation.
10. The channel interface module of claim 9 , wherein each of said bitwise multiplexers receives a corresponding representation bit from each tentative symbol decision, and the corresponding representation bits are provided as a thermometer-coded representation of an input value.
11. The channel interface module of claim 10 , wherein each of the bitwise multiplexers consists of parallel circuit paths between an output node and a common node, each path having at most one selection bit controlled transistor in series with at most one input bit controlled transistor.
12. The channel interface module of claim 11 , wherein the thermometer-coded representations of the tentative symbol decisions, the preceding symbol decision, and the current symbol decision, each have a least significant bit, one or more intermediate significance bits, and a most significant bit.
13. The channel interface module of claim 12 , wherein one of the parallel circuit paths has a least significant bit of the preceding symbol decision controlling a transistor in series with a transistor controlled by a least significant bit of the input value.
14. The channel interface module of claim 12 , wherein one of the parallel circuit paths has a most significant bit of the preceding symbol decision controlling a transistor in series with a transistor controlled by a most significant bit of the input value.
15. The channel interface module of claim 9 , wherein the receiver further includes: a front end filter that processes a receive signal to produce a filtered signal having reduced leading intersymbol interference; and a feedback filter that derives a feedback signal from past symbol decisions to reduce trailing intersymbol interference.
16. The channel interface module of claim 9 , wherein the tentative symbol decisions are chosen from a pulse amplitude modulation (PAM) constellation having at least four symbol values.
17. A decision feedback equalizer (DFE) comprising: a precompensation unit that produces at each of multiple time intervals a set of thermometer-coded tentative symbol decisions, each thermometer-coded tentative symbol decision accounting for trailing intersymbol interference from a speculative preceding symbol value; bitwise multiplexers each operating on corresponding bits from the set of thermometer-coded tentative symbol decisions, the corresponding bits for each bitwise multiplexer forming a thermometer-coded input value; and a latch that captures outputs from the bitwise multiplexers as a thermometer-coded current symbol decision, and that provides a thermometer-coded preceding symbol decision as a selection value to each of the bitwise multiplexers.
18. The DFE selection unit of claim 17 , wherein each of the bitwise multiplexers consists of parallel circuit paths between an output node and a common node, each path having at most one selection bit controlled transistor in series with at most one input bit controlled transistor.
19. The DFE selection unit of claim 18 , wherein the thermometer-coded tentative symbol decisions, the thermometer-coded preceding symbol decision, and the thermometer-coded current symbol decision, each have a least significant bit, one or more intermediate significance bits, and a most significant bit.
20. The DFE selection unit of claim 19 , wherein one of the parallel circuit paths has a least significant bit of the thermometer-coded preceding symbol decision controlling a transistor in series with a transistor controlled by a least significant bit of the thermometer-coded input value.
21. The DFE selection unit of claim 19 , wherein one of the parallel circuit paths has a most significant bit of the thermometer-coded preceding symbol decision controlling a transistor in series with a transistor controlled by a most significant bit of the thermometer-coded input value.
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December 6, 2018
June 9, 2020
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