A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor chip module comprising: a chip package including a substrate, a processor disposed on the substrate in a central region of the substrate, a plurality of active chips disposed on the substrate around the processor, a plurality of dummy chips disposed on the substrate in spaces between the plurality of active chips, and epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate; and a printed circuit board (PCB) to which the chip package is mounted, wherein each of the dummy chips comprises a chip body having an upper surface, and the semiconductor chip module has channels of the epoxy resin interposed between the upper surface of the chip body of each of the dummy chips and the substrate of the chip package.
2. The semiconductor chip module of claim 1 , wherein for each of the dummy chips, a plurality of channels of the epoxy resin is interposed between the upper surface of the chip body of each of the dummy chip and the substrate of the chip package, the channels extending parallel to each other in a direction of an axis parallel to a side of the chip body of the dummy chip.
3. The semiconductor chip module of claim 1 , wherein for each of the dummy chips, a plurality of channels of the epoxy resin is interposed between the upper surface of the chip body of the dummy chip and the substrate of the chip package, the channels extending diagonally relative to sides of the chip body of the dummy chip.
4. The semiconductor chip module of claim 1 , wherein for each of the dummy chips, a plurality of channels of the epoxy resin extend within the dummy chip between an uppermost surface of the chip body and a lowermost surface of the chip body of the dummy chip.
5. The semiconductor chip module of claim 4 , wherein the PCB is convex towards the chip package, and the channels extend in bottom portions of the dummy chips adjacent to the substrate of the chip package.
6. The semiconductor chip module of claim 4 , wherein the PCB is substantially flat, and the channels extend midway between the uppermost surfaces and lowermost surfaces of the chip bodies of the dummy chips in vertically central portions of the dummy chips.
7. The semiconductor chip module of claim 4 , wherein the PCB is concave towards the chip package, and the channels extend in top portions of the dummy chips remote from the substrate of the chip package.
8. A semiconductor chip module comprising: a chip package including a substrate having an upper surface, a processor disposed on the substrate in a central region of the upper surface of the substrate, a plurality of active chips disposed on the upper surface of the substrate around the processor, a plurality of dummy chips disposed on the upper surface substrate in spaces between the plurality of active chips, and epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate at the upper surface of the substrate; and a printed circuit board (PCB) having an upper surface to which the chip package is mounted, wherein each of the dummy chips comprises a chip body having an upper surface, the semiconductor chip module has a plurality of first channels of the epoxy resin and a plurality of second channels of the epoxy resin interposed between the upper surface of the chip body of each of the dummy chips and the substrate of the chip package, the first channels extend longitudinally in a first axial direction and the second channels extend longitudinally in a second axial direction different from the first axial direction, and the first channels are spaced a predetermined distance apart from the plurality of second channels in a vertical direction perpendicular to the upper surface of the substrate of the chip package.
9. The semiconductor chip module of claim 8 , wherein the first and second axial directions are orthogonal.
10. The semiconductor chip module of claim 9 , wherein in each of the dummy chips the plurality of first channels extend in one of a bottom portion, a central portion, and a top portion of the dummy chip relative to the substrate of the chip package, and the second channels also extend in said one of the bottom portion, central portion, and top portion of the dummy chip.
11. The semiconductor chip module of claim 10 , wherein the PCB is convex towards the chip package, and in each of the dummy chips, the plurality of first channels and the plurality of second channels extend in the bottom portion of the dummy chip.
12. The semiconductor chip module of claim 10 , wherein the PCB is substantially flat, and in each of the dummy chips, the plurality of first channels and the plurality of second channels extend in the central portion of each of the dummy chip.
13. The semiconductor chip module of claim 10 , wherein the PCB is concave towards the chip package, and in each of the dummy chips, the plurality of first channels and the plurality of second channels extend in the top portion of the dummy chip.
14. The semiconductor chip module of claim 9 , wherein in each of the dummy chips the plurality of first channels extend in a bottom portion of the dummy chip adjacent to the substrate of the chip package, and the plurality of second channels extend midway between an uppermost surface of the chip body of the dummy chip and a lowermost surface of the chip body in a central portion of the dummy chip.
15. The semiconductor chip module of claim 9 , wherein in each of the dummy chips the plurality of first channels extend in a bottom portion of the dummy chip adjacent to the substrate of the chip package, and the second channels extend in a top portion of the dummy chip remote from the substrate of the chip package.
16. The semiconductor chip module of claim 9 , wherein in each of the dummy chips the plurality of first channels extend midway between an uppermost surface of the chip body of the dummy chip and a lowermost surface of the chip body in a central portion of the dummy chip, and the second channels extend in a top portion of each of the dummy chip remote from the substrate of the chip package.
17. The semiconductor chip module of claim 8 , wherein in each of the dummy chips the first channels each extend longitudinally in a diagonal direction relative to sides of the chip body of the dummy chip, and the second channels each extend longitudinally at a right angle to the diagonal direction.
18. The semiconductor chip module of claim 8 , wherein in each of the dummy chips the first channels each extend longitudinally in a direction perpendicular to a side of the chip body of the dummy chip, and the second channels each extend longitudinally in a diagonal direction relative to said side of the chip body of the dummy chip.
19. A semiconductor chip module comprising: a chip package including a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed on the substrate around the processor, a plurality of dummy chips disposed on the substrate in spaces between the plurality of active chips, a plurality of dummy bump joints interposed between each of the dummy chips and the substrate, and an epoxy resin configured to package the plurality of active chips and the plurality of dummy chips; and a printed circuit board (PCB) to which the chip package is mounted, wherein each of the dummy chips comprises a chip body having an upper surface, the plurality of dummy bump joints are spaced laterally from each other to define spaces therebetween, and the spaces between the dummy bump joints are filled with the epoxy resin such that channels of the epoxy resin are interposed between the upper surface of the chip body of each of the dummy chips and the substrate of the chip package.
20. The semiconductor chip module of claim 19 , wherein the channels of the epoxy resin have the form of a lattice such that first ones of the channels between the upper surface of the chip body of each of the dummy chips and the substrate of the chip package each extend longitudinally in a first axial direction and second ones of the channels between the upper surface of the chip body of each of the dummy chips and the substrate of the chip package each extend longitudinally in a second axial direction orthogonal to the first axial direction.
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November 23, 2018
June 16, 2020
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