Patentable/Patents/US-10698617
US-10698617

Memory system

PublishedJune 30, 2020
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

According to one embodiment, a memory system includes: a non-volatile memory including a first area configured to hold first data received from an outside and a second area configured to hold second data; a volatile memory; and a controller. The non-volatile memory holds third data that associates a first address of the first data assigned to an instruction received from an outside with a second address of the first data that specifies a part of the first area. As a startup operation, the controller reads the third data from the non-volatile memory and holds the third data as fourth data in the volatile memory. The controller erases the fourth data from the volatile memory when the second data is held in the second area.

Patent Claims
9 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A memory system comprising: a non-volatile memory including a first area configured to hold first data received from an outside and a second area configured to hold second data; a volatile memory; and a controller configured to control the non-volatile memory and the volatile memory, wherein the non-volatile memory holds third data that associates a first address of the first data with a second address of the first data, the first address being assigned to an instruction received from an outside, the second address specifying a part of the first area, as a startup operation, the controller reads the third data from the non-volatile memory and holds the third data as fourth data in the volatile memory, and the controller erases the fourth data from the volatile memory when the second data is held in the second area.

2

2. The system according to claim 1 , wherein when receiving an erase instruction from an outside, the controller erases the fourth data from the volatile memory, and instructs the non-volatile memory to write the second data into the second area.

3

3. The system according to claim 2 , wherein the non-volatile memory includes a first mode and a second mode, the first mode restricting a write operation and an erase operation, the second mode restricting neither the write operation nor the erase operation, in the first mode, the controller instructs the non-volatile memory to write the second data, and in the second mode, the controller instructs the non-volatile memory to erase the third data held in the non-volatile memory.

4

4. The system according to claim 1 , wherein the second area includes a third area that holds the second data, and a fourth area that holds the third data.

5

5. The system according to claim 1 , wherein the non-volatile memory is a NAND-type flash memory.

6

6. The system according to claim 1 , wherein the second data is information indicating that the fourth data has been erased.

7

7. The system according to claim 1 , wherein when the fourth data is held in the volatile memory after the startup operation, the controller reads the first data from the non-volatile memory based on a read instruction of the first data, and when the fourth data is not held in the volatile memory after the startup operation, the controller does not perform a read operation in the non-volatile memory.

8

8. The system according to claim 1 , wherein when the second data is held in the second area in the startup operation, the controller erases the fourth data from the volatile memory, instead of reading the third data from the non-volatile memory, and when the second data is not held in the second area in the startup operation, the controller reads the third data from the non-volatile memory and holds the third data as the fourth data in the volatile memory.

9

9. A memory system comprising: a first non-volatile memory including a first area configured to hold first data received from an outside; a second non-volatile memory including a second area configured to hold second data; a volatile memory; and a controller configured to control the first and second non-volatile memories and the volatile memory, wherein the non-volatile memory holds third data that associates a first address of the first data with a second address of the first data, the first address being assigned to an instruction received from an outside, the second address specifying a part of the first area, as a startup operation, the controller reads the third data from the second non-volatile memory and holds the third data as fourth data in the volatile memory, and the controller erases the fourth data from the volatile memory when the second data is held in the second area.

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Patent Metadata

Filing Date

March 6, 2019

Publication Date

June 30, 2020

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Cite as: Patentable. “Memory system” (US-10698617). https://patentable.app/patents/US-10698617

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