An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating a radio frequency (RF) device on a silicon-on-insulator (SOI) substrate, the method comprising: forming an NMOS transistor on a device layer of said SOI substrate such that said NMOS transistor includes first and second source/drain regions separated by a channel region in said device layer, and such that said NMOS transistor includes a polycrystalline silicon gate structure disposed over said channel region; forming first and second silicide structure on the first and second source/drain regions, respectively; forming a triple-layer stressing stack over the polycrystalline silicon gate structure and the first and second silicide structures such that the triple-layer stressing stack includes a stressor layer configured to generate a tensile mechanical stress in the channel region, an intermediate buffer layer disposed on an upper surface of the stressor layer, and an upper etch-stop layer disposed on an upper surface of the intermediate buffer layer; forming a first dielectric layer over the triple-layer stressing stack; and forming a low-dielectric-constant (low-k) feature in said first dielectric layer by removing a portion of the first dielectric layer and a portion of said upper etch-stop layer of said triple-layer stressing stack to form an air gap region located over the polycrystalline silicon gate structure.
2. The method of claim 1 , wherein the device layer of said SOI substrate has a thickness in the range of 200 Angstroms to 2000 Angstroms, wherein the method further comprises separating said device layer into a plurality of electrically isolated silicon islands, and wherein said forming the NMOS transistor comprises forming said NMOS transistor on an associated silicon island of said plurality of silicon islands.
3. The method of claim 2 , wherein forming the stressor layer comprises depositing a first dielectric material such that said deposited first dielectric material has a first residual tensile stress level that generates said tensile mechanical stress in the channel region, and wherein forming the upper etch-stop layer comprises depositing a second dielectric material such that said deposited second dielectric material has a second residual tensile stress level that is lower than said first residual tensile stress level.
4. The method of claim 3 , further comprising: performing a first etching process to form first and second openings that respectively extend vertically through said first dielectric layer to first and second silicide structures respectively formed on said first and second source/drain regions; forming first and second metal contact/via structures in said first and second openings such that said first and second metal contact/via structures extend vertically through said first dielectric layer and contact said first and second silicide structures; forming a second dielectric layer over said first dielectric layer and said first and second interconnect lines; and forming first and second metal interconnect lines in said second dielectric layer over said first dielectric layer such that said first and second metal interconnect lines are disposed over and operably connected to said first and second metal contact/via structure, respectively, wherein forming said low-k feature comprises performing a second etching process such that a portion of said second dielectric layer is removed before removing said portions of said first dielectric layer and said upper etch-stop layer.
5. The method of claim 4 , further comprising forming a first etch-stop layer on an upper surface of said first dielectric layer before forming said second dielectric layer, and forming a second etch-stop layer on an upper surface of said second dielectric layer after forming said first and second metal interconnect lines, wherein forming said first and second metal interconnect lines comprises depositing copper.
6. The method of claim 5 , wherein performing said second etching process comprises: performing a first anisotropic dry etch to remove a portion of said second etch-stop layer located over said portion of said second dielectric layer, to remove said portion of said second dielectric layer, and to remove a portion of said first etch-stop layer located under said portion of said second dielectric layer, thereby forming an upper air gap section over said polycrystalline silicon gate structure; performing an isotropic dry etch through said upper air gap section to remove said portion of said first dielectric layer, thereby forming an intermediate air gap section over said polycrystalline silicon gate structure having a horizontal dimension in the range of 0.16 Angstroms to 0.34 Angstroms; and performing a second anisotropic dry etch to remove said portion of said upper etch-stop layer.
7. A method of claim 6 , wherein forming said low-k feature further comprises depositing a low-conformity dielectric material over said second dielectric layer such that said low-conformity dielectric material forms a third dielectric layer that seals said the air gap region.
8. A method of claim 7 , further comprising forming a capping dielectric layer over the third dielectric layer using a low-moisture-penetration material such that said capping dielectric layer protects said the air gap region from moisture penetration.
9. The method of claim 3 , wherein forming the lower dielectric layer comprises depositing a layer of one of Silicon Nitride and Oxynitride having a thickness T 2 in the range of 500 Angstroms to 2000 Angstroms.
10. The method of claim 9 , wherein forming the intermediate buffer layer comprises forming a layer of silicon dioxide having a thickness in the range of 10 Angstroms to 600 Angstroms.
11. The method of claim 10 , wherein forming said upper etch-stop layer comprises forming one of a Silicon Nitride layer and an a-SiC:H material layer having a thickness in the range of 100 Angstroms to 600 Angstroms.
12. The method of claim 4 , wherein performing said second etching process comprises: performing a first anisotropic dry etch to remove said portion of said second dielectric layer; performing an isotropic dry etch to remove said portion of said first dielectric layer; and performing a second anisotropic dry etch to remove said portion of said upper etch-stop layer.
13. The method of claim 12 , wherein performing the isotropic dry etch comprises forming an intermediate air gap section in said first dielectric layer having a horizontal dimension in the range of 0.16 Angstroms to 0.34 Angstroms.
14. The method of claim 1 , wherein forming said low-k feature further comprises depositing a low-dielectric-constant material such that said low-dielectric-constant material fills said air gap region.
15. The method of claim 14 , further comprises depositing a sealing material over said second dielectric layer such that said sealing material forms a sealing layer that covers an upper boundary of said low-k feature.
16. A method for fabricating a radio frequency (RF) device on a silicon-on-insulator (SOI) substrate, the method comprising: forming an NMOS transistor on a device layer of said SOI substrate such that said NMOS transistor includes first and second source/drain regions separated by a channel region in said device layer, and such that said NMOS transistor includes a polycrystalline silicon gate structure disposed on an upper surface of the device layer over said channel region; forming a stressor layer over the polycrystalline silicon gate structure and the first and second source/drain regions such that the stressor layer includes a first residual tensile stress level that generates a tensile mechanical stress in the channel region; forming a buffer layer over the stressor layer; forming an etch-stop layer over the buffer layer such that the etch-stop layer has a second residual tensile stress level that is lower than the first residual tensile stress level; forming a first dielectric layer over the etch-stop layer; performing a first etching process to define contact/via openings that extend through the first dielectric layer, the stressor layer, the buffer layer, and the etch-stop layer to upper portions of the device layer disposed over the first and second source/drain regions; performing a second etching process to define an air gap region that extends through a portion of the first dielectric layer that is located over the polycrystalline silicon gate structure, wherein said second etching process is terminated when a lower boundary of said air gap region is located between an upper surface of said etch-stop layer and an upper surface of said stressor layer; and forming a sealing layer over an upper end of said air gap region.
17. A radio frequency (RF) silicon-on-insulator (SOI) device formed on a device layer of an SOI substrate, the RF SOI device comprising: first and second source/drain regions disposed in the device layer and separated by a channel region; a polycrystalline silicon (polysilicon) gate structure disposed over the channel region; first and second silicide structures disposed on an upper surface of the device layer over the first and second source/drain regions, respectively; a triple-layer stressing structure disposed over the polysilicon gate structure and the first and second silicide structures, said triple-layer stressing stack including a stressor layer having a first residual tensile stress level that generates a tensile mechanical stress in the channel region, an intermediate buffer layer disposed on an upper surface of the stressor layer, and an upper etch-stop layer disposed on an upper surface of the intermediate buffer layer, wherein the upper etch-stop layer has a second residual tensile stress level that is lower than said first residual tensile stress level; a first dielectric layer disposed on an upper surface of the triple-layer stressing structure, and a second dielectric layer disposed over the first dielectric layer, said first and second dielectric layers consisting essentially of one or more dielectric materials having a nominal first dielectric constant; and a low-dielectric-constant (low-k) feature disposed in said first dielectric layer over said polysilicon gate structure such that a lower boundary of said low-k feature extends into a portion of said upper etch-stop layer, wherein said low-k feature comprises one of a low-k material and a void region such that a second dielectric constant of said low-k feature is lower than said first dielectric constant of said at least one dielectric layer.
18. The RF SOI device of claim 17 , wherein said RF SOI device comprises an RF SOI switch circuit.
19. The RF SOI device of claim 17 , wherein said RF SOI device comprises an RF SOI power amplifier.
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April 3, 2019
July 7, 2020
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