Semiconductor integrated circuit

1. A semiconductor integrated circuit comprising: first to fifth wiring lines; a first OTP memory element including a first terminal connected to the first wiring line and a second terminal connected to the second wiring line; a first p-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a first control signal; a first n-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the fourth wiring line, and a gate terminal, which receives a second control signal; a second p-channel transistor including a source terminal and a drain terminal, one of which is connected to the second wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a third control signal; and a second n-channel transistor including a source terminal and a drain terminal, one of which is connected to the second wiring line and the other of which is connected to the fifth wiring line, and a gate terminal, which receives a fourth control signal.

2. The semiconductor integrated circuit according to claim 1 , further comprising a selection circuit including a first input terminal, a second input terminal, and a first output terminal connected to the fifth wiring line, the selection circuit electrically connecting one of the first input terminal and the second input terminal to the first output terminal in accordance with an enable signal.

3. The semiconductor integrated circuit according to claim 1 , wherein the first OTP memory element includes a MOS transistor, in which the first terminal is a gate terminal and the second terminal is source and drain terminals that are electrically connected to each other of the MOS transistor, or the first terminal is the source and drain terminals that are electrically connected each other and the second terminal is the gate terminal of the MOS transistor.

4. The semiconductor integrated circuit according to claim 1 , further comprising a driver configured to: turn on the first p-channel transistor and the second n-channel transistor based on the first control signal and the fourth control signal, and turn off the first n-channel transistor and the second p-channel transistor based on the second control signal and the third control signal so as to set a potential applied to the third wiring line to be higher than a potential applied to the fifth wiring line to apply a write voltage between the third wiring line and the fifth wiring line, thereby writing data to the first OTP memory element; and turn on the first n-channel transistor and the second p-channel transistor based on the second control signal and the third control signal, and turn off the first p-channel transistor and the second n-channel transistor based on the first control signal and the fourth control signal so as to set the potential applied to the third wiring line to be higher than a potential applied to the fourth wiring line to apply a write voltage between the third wiring line and the fourth wiring line, thereby writing data to the first OTP memory element.

5. The semiconductor integrated circuit according to claim 1 , further comprising: a sixth wiring line and a seventh wiring line; a second OTP memory element including a third terminal connected to the sixth wiring line and a fourth terminal connected to the second wiring line; a third p-channel transistor including a source terminal and a drain terminal, one of which is connected to the sixth wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a fifth control signal; and a third n-channel transistor including a source terminal and a drain terminal, one of which is connected to the sixth wiring line and the other of which is connected to the seventh wiring line, and a gate terminal, which receives the second control signal.

6. The semiconductor integrated circuit according to claim 5 , wherein when a write operation is performed on the second OTP memory element, the driver turns on the third p-channel transistor and the second n-channel transistor based on the fifth control signal and the fourth control signal, and turns off the third n-channel transistor and the second p-channel transistor based on the second control signal and the third control signal so as to set a potential applied to the third wiring line to be higher than a potential applied to the fifth wiring line to apply a write voltage between the third wiring line and the fifth wiring line, thereby writing data to the second OTP memory element and turns on the third n-channel transistor and the second p-channel transistor based on the second control signal and the third control signal and turns off the third p-channel transistor and the second n-channel transistor based on the fifth control signal and the fourth control signal so as to set the potential applied to the third wiring line to be higher than a potential applied to the seventh wiring line to apply a write voltage between the third wiring line and the seventh wiring line.

7. The semiconductor integrated circuit according to claim 5 , wherein the second OTP memory element includes a MOS transistor, and wherein the third terminal is a gate terminal and the fourth terminal is the source and drain terminals that are electrically connected to each other of the MOS transistor, or the third terminal is the source and drain terminals that are electrically connected to each other and the fourth terminal is the gate terminal of the MOS transistor.

8. A semiconductor integrated circuit comprising: first to fourth wiring lines; a first OTP memory element including a first terminal connected to the first wiring line and a second terminal connected to the second wiring line; a first p-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a first control signal; and a first n-channel transistor including a source terminal and a drain terminal, one of which is connected to the first wiring line and the other of which is connected to the fourth wiring line, and a gate terminal, which receives a second control signal.

9. The semiconductor integrated circuit according to claim 8 , further comprising a selection circuit including a first input terminal, a second input terminal, and a first output terminal electrically connected to the second wiring line, the selection circuit electrically connecting one of the first input terminal and the second input terminal to the first output terminal in accordance with an enable signal.

10. The semiconductor integrated circuit according to claim 8 , wherein: the first OTP memory element includes a MOS transistor in which the first terminal is a gate terminal and the second terminal is source and drain terminals that are electrically connected to each other of the MOS transistor, or the first terminal is the source and drain terminals that are electrically connected to each other and the second terminal is the gate terminal of the MOS transistor.

11. The semiconductor integrated circuit according to claim 8 , further comprising a driver configured to: turn on the first p-channel transistor based on the first control signal, and turn off the first n-channel transistor based on the second control signal so as to set a potential applied to the third wiring line to be higher than a potential applied to the second wiring line to apply a write voltage between the third wiring line and the second wiring line, thereby writing data to the first OTP memory element; and turn on the first n-channel transistor based on the second control signal and turn off the first p-channel transistor based on the first control signal so as to set a potential applied to the fourth wiring line to be lower than the potential applied to the second wiring line to apply a write voltage between the fourth wiring line and the second wiring line, thereby writing data to the first OTP memory element.

12. The semiconductor integrated circuit according to claim 8 , further comprising: a fifth wiring line; a second OTP memory element including a third terminal connected to the fifth wiring line and a fourth terminal connected to the second wiring line; a second p-channel transistor including a source terminal and a drain terminal, one of which is connected to the fifth wiring line and the other of which is connected to the third wiring line, and a gate terminal, which receives a third control signal; and a second n-channel transistor including a source terminal and a drain terminal, one of which is connected to the fifth wiring line and the other of which is connected to the fourth wiring line, and a gate terminal, which receives a fourth control signal.

13. The semiconductor integrated circuit according to claim 12 , wherein when a write operation is performed on the second OTP memory element, the driver turns on the second p-channel transistor based on the third control signal, and turns off the second n-channel transistor based on the fourth control signal so as to set a potential applied to the third wiring line to be higher than a potential applied to the second wiring line to apply a write voltage between the third wiring line and the second wiring line, thereby writing data to the second OTP memory element, and turns on the second n-channel transistor based on the fourth control signal and turns off the second p-channel transistor based on the third control signal so as to set a potential applied to the fourth wiring line to be lower than the potential applied to the second wiring line to apply a write voltage between the fourth wiring line and the second wiring line, thereby writing data to the second OTP memory element.

14. The semiconductor integrated circuit according to claim 12 , wherein the second OTP memory element includes a MOS transistor, in which the third terminal is a gate terminal and the fourth terminal is source and drain terminals that are electrically connected to each other of the MOS transistor, or the third terminal is the source and drain terminals that are electrically connected to each other and the fourth terminal is the gate terminal of the MOS transistor.