A superconducting field programmable gate array (SuperFPGA) apparatus for implementing a superconducting electronic circuit includes a superconducting logic core that includes a plurality of superconducting single flux quantum configurable logic blocks having regular Josephson junctions and inductors that are interconnectible to each other and to input/output terminals of the superconducting electronic circuit. The SuperFPGA apparatus also includes a superconducting routing network, a zero-static-power dissipation biasing network, magnetic Josephson junctions, and a magnetic Josephson junction programming layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A superconducting field programmable gate array (SuperFPGA) apparatus for implementing a superconducting electronic circuit, comprising: a superconducting logic core comprising a plurality of superconducting single flux quantum configurable logic blocks that includes regular Josephson junctions and inductors that are interconnectible to each other and to input/output terminals of the superconducting electronic circuit; a superconducting routing network comprising a collection of transmission lines, programmable connection blocks, and programmable switchboxes for realizing connections among the superconducting single flux quantum configurable logic blocks and input/output terminals; a zero-static-power dissipation biasing network for supplying desired amounts of biasing currents to the superconducting logic core and superconducting routing network; magnetic Josephson junctions used selectively in the zero-static-power dissipation biasing network to enable in-field programmability of the said superconducting logic core and superconducting routing network by changing amounts of locally-provided biasing currents; and a magnetic Josephson junction programming layer comprising of decoders and superconducting current-carrying lines to enable and effect selective setting of critical current levels of the magnetic Josephson junctions.
2. The SuperFPGA apparatus of claim 1 wherein circuit operates in a synchronous or asynchronous manner.
3. The SuperFPGA apparatus of claim 1 wherein the superconducting single flux quantum configurable logic blocks are programmable to perform a specific Boolean operation by changing biasing currents through the magnetic Josephson junction programming layer.
4. The SuperFPGA apparatus of claim 1 wherein the superconducting single flux quantum configurable logic blocks are look-up table based or a function selectable type.
5. The SuperFPGA apparatus of claim 4 wherein a lookup table based superconducting single flux quantum configurable logic block comprises: a decoder that can decode a maximum number of inputs that a logic gate can have; a plurality of magnetic Josephson junction-containing switches placed at each decoder output to selectively block or pass decoded outputs, each switch comprising regular and magnetic Josephson junctions and inductors; and a merge-block that merges the decoded outputs to realize Boolean function of the said logic gate at an output of the superconducting single flux quantum configurable logic blocks.
6. The SuperFPGA apparatus of claim 4 wherein a function selectable based superconducting single flux quantum configurable logic block comprises: a plurality of a predetermined number of gates; a plurality of splitters with switches that carry inputs to each of the gates, each splitter having a magnetic Josephson junction-containing switch at each splitter output, each switch comprising regular and magnetic Josephson junctions and inductors to selectively block or pass signals; and a merger circuit that mergers outputs from the gates to give a configurable logic block output.
7. The SuperFPGA apparatus of claim 1 wherein the programmable connection blocks and programmable switchboxes are programmable to provide selective connectivity among input or output routing channels and configurable logic blocks by the magnetic Josephson junction programming layer.
8. The SuperFPGA apparatus of claim 7 wherein the programmable switchboxes include splitters having a splitter input and 2 or more splitter outputs, each splitter output is directly connected to a magnetic Josephson junction-containing switch.
9. The SuperFPGA apparatus of claim 8 wherein the programmable switchboxes include merger circuits that combines 2 or more input signals into a merged output signal.
10. The SuperFPGA apparatus of claim 1 wherein the superconducting logic core is organized as a regular two-dimensional array of superconducting Single flux quantum configurable logic blocks.
11. The SuperFPGA apparatus of claim 1 wherein the superconducting routing network allows signal flow in horizonal or vertical directions in unidirectional or bidirectional manner.
12. The SuperFPGA apparatus of claim 1 wherein outputs of vertical connection blocks are routed to inputs of configurable logic blocks and outputs of the superconducting single flux quantum configurable logic blocks are routed to inputs of horizontal connection blocks.
13. The SuperFPGA apparatus of claim 3 wherein the superconducting routing network comprises vertical and horizontal connection blocks such that vertical connection blocks receive input data from connected vertical routing channels and selectively send output data to connected configurable logic block and horizontal connection blocks selectively connect horizontal channels to nearby configurable logic blocks.
14. The SuperFPGA apparatus of claim 1 wherein passive and Josephson transmission lines may be included in horizontal and vertical connection blocks.
15. The SuperFPGA apparatus of claim 1 wherein the zero-static-power dissipation biasing network is an energy-efficient rapid single flux quantum biasing network.
16. The SuperFPGA apparatus of claim 1 , wherein magnetic Josephson junctions are placed in an array where programming of their critical current level is achieved by controlling current flow through current-carrying lines of a cross-bar structure with each intersection points of the cross-bar corresponding to a specific magnetic Josephson junction of the array.
17. The SuperFPGA apparatus of claim 16 wherein the superconducting routing network allows signal flow in horizonal or vertical directions of the array in unidirectional or bidirectional manner.
18. The SuperFPGA apparatus of claim 2 wherein distribution of clock pulses for synchronous circuit operation is achieved by various clock distribution schemes, including zero-skew, concurrent flow, counter flow, and clock-follow-data.
19. The SuperFPGA apparatus of claim 18 wherein the superconducting logic core as organized as a regular two-dimensional array of superconducting single flux quantum configurable logic blocks.
20. The SuperFPGA apparatus of claim 19 wherein clock pulse distribution for synchronous operation is achieved using a clock-follow-data scheme such that logic circuits including logic gates are each mapped to a configurable logic block in the superconducting logic core in such a way that logic gates with a same logical depth lie in one or more consecutive columns of the regular two-dimensional array of superconducting single flux quantum configurable logic blocks.
21. The SuperFPGA apparatus of claim 18 wherein a clock-follow-data scheme can be used for reset-pulse distribution in case of operation in an asynchronous wave-pipelined manner.
22. A method of enabling in-field programmability of a superconducting field programmable logic circuit, comprising: receiving programming data describing a desired functionality of the superconducting field programmable logic circuit; decoding the programming data to produce a bit stream for programming individual configurable logic blocks and interconnections among configurable logic blocks and primary inputs/outputs of the superconducting field programmable logic circuit; and processing the bit stream by selectively changing a magnitude of a current flowing in a superconducting line to cause a change in a critical current level of a nearby magnetic Josephson junction, the change causing a corresponding a change in biasing current level supplied to a target superconducting programmable logic or interconnect element wherein the interconnections that are programmed include programmable connection blocks and programmable switchboxes that are programmable to provide selective connectivity among input or output routing channels and configurable logic blocks.
23. The method of claim 22 wherein individual logic cells are programmed includes superconducting single flux quantum configurable logic blocks that are interconnectible to each other and to input/output terminals of the superconducting field programmable logic circuit.
24. The method of claim 23 wherein the superconducting single flux quantum configurable logic blocks are programmable to perform a specific Boolean operation.
25. The method of claim 24 wherein the superconducting single flux quantum configurable logic blocks are look-up table based or a function selectable type.
26. The method of claim 25 wherein a lookup table based superconducting single flux quantum configurable logic block comprises: a decoder that can decode a maximum number of inputs that a logic gate can have; a plurality of magnetic Josephson junctions such that a magnetic Josephson junction-containing switches placed at each decoder output to selectively block or pass decoded outputs, each switch comprising regular and magnetic Josephson junctions and inductors; and a merge-block that merges the decoded outputs to realize Boolean function of the logic gate at an output of the superconducting single flux quantum configurable logic blocks.
27. The method of claim 25 wherein a function selectable based superconducting single flux quantum configurable logic block comprises: a plurality of a predetermined number of gates; a plurality of splitters with switches that carry inputs to each of the gates, each splitter having a magnetic Josephson junction-containing switch at each splitter output, each switch comprising regular and magnetic Josephson junctions and inductors to selectively block or pass signals; and a merger circuit that mergers outputs from the gates to give a configurable logic block output.
28. The method of claim 22 wherein the programmable switchboxes include splitters having a splitter input and 2 or more splitter outputs, each splitter output being direct to a magnetic Josephson junction-containing switch.
29. The method of claim 22 wherein the programmable switchboxes include merger circuits that combines 2 or more input signals into a merged output signal.
30. The method of claim 27 wherein the function selectable based superconducting single flux quantum configurable logic block implements non-combinational logic gates such as a Muller C-element.
31. The method of claim 27 wherein the superconducting field programmable logic circuit also includes configurable logic blocks producing more than one output.
32. The method of claim 22 wherein program decoders used for decoding programming data to produce the bit stream for programming individual configurable logic blocks and interconnections among configurable logic blocks and primary inputs/outputs of the superconducting field programmable logic circuit can be either single-flux quantum based or CMOS based circuits.
33. The method of claim 32 wherein inputs to the program decoders can be provided either in parallel or serially.
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March 21, 2019
July 7, 2020
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