An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: physical layer (PHY) circuitry; a memory to implement a message bus register, wherein a set of control and status signals are mapped to bits of the message bus register, and the set of control and status signals comprises a recalibration request signal mapped to a particular one of the bits of the message bus register; and an interface to couple to a controller, wherein the interface comprises a PHY Interface for the PCI Express (PIPE)-based interface, and the interface comprises: a set of data pins comprising transmit data pins to send data to the controller and receive data pins to receive data from the controller; a particular set of pins to implement a message bus interface, wherein a write command is to be received from the controller over the message bus interface to write a value to the particular bit; and recalibration circuitry to perform a recalibration of the PHY circuitry based on the value written to the particular bit.
2. The apparatus of claim 1 , wherein the write command comprises a committed write.
3. The apparatus of claim 1 , wherein the value of the particular bit is to be reset automatically after a number of clock cycles.
4. The apparatus of claim 1 , further comprising detection circuitry to: detect one or more attributes of the PHY circuitry; and determine that the recalibration should be performed based on the one or more attributes.
5. The apparatus of claim 4 , wherein the PHY circuitry is to send a write command to the controller over the message bus interface to write a value to a message bus register of the controller to indicate to the controller a request to perform the recalibration.
6. The apparatus of claim 5 , wherein the write command from the controller is received based on the request to perform the recalibration.
7. The apparatus of claim 6 , wherein the PHY circuitry is to implement a link and the recalibration is to be performed while the link is in recovery, wherein the controller is to initiate the recovery.
8. The apparatus of claim 1 , wherein the PHY circuitry is to send a write command to the controller over the message bus interface to write a value to a message bus register of the controller to indicate to the controller that the recalibration is complete.
9. The apparatus of claim 1 , wherein the PIPE-based interface comprises a PHY Interface for PCI Express, SATA, DisplayPort, and Converged IO Architectures.
10. An apparatus comprising: a controller; and an interface to couple the controller to a physical layer (PHY) block, wherein the interface comprises: a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block; a particular set of pins to implement a message bus interface, wherein the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.
11. The apparatus of claim 10 , wherein the set of control and status signals comprises a first set of control and status signals, and the apparatus further comprises a memory to implement a controller message bus register, wherein bits of the controller message bus register are mapped to a second set of control and status signals, and the controller is to receive commands from the PHY block over the message bus interface to set values of bits in the controller message bus register to indicate particular signals in the second set of control and status signals.
12. The apparatus of claim 11 , wherein the second set of control and status signals comprises a recalibration complete signal mapped to a particular one of the bits of the controller message bus register to indicate completion of the recalibration by the PHY block.
13. The apparatus of claim 11 , wherein the second set of control and status signals comprises a PHY-initiated recalibration request signal mapped to a particular one of the bits of the controller message bus register to initiate the recalibration by the PHY block.
14. The apparatus of claim 13 , wherein the recalibration is to be performed while a link is in recovery, the controller is to initiate transition of the link to recovery, and the PHY-initiated recalibration request signal is to request the controller to initiate the transition of the link to recovery.
15. The apparatus of claim 13 , wherein the second set of control and status signals further comprises a recalibration complete signal mapped to another one of the bits of the controller message bus register to indicate completion of the recalibration by the PHY block.
16. The apparatus of claim 10 , wherein the interface comprises a PHY Interface for the PCI Express (PIPE)-based interface.
17. The apparatus of claim 10 , wherein the controller comprises a media access controller (MAC).
18. A system comprising: a first device comprising a media access controller (MAC) circuitry; a second device comprising physical layer (PHY) circuitry, wherein the second device comprises a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and a particular one of the bits of the PHY message bus register is mapped to a recalibration request signal; an interface to couple the first device to the second device, wherein the interface comprises: a first pins to enable signaling of data from the first device to the second device; second pins to enable signaling of data from the second device to the first device; third pins to implement a message bus interface, wherein the first device is to send a write request to the second device over the message bus interface to write a value to the particular bit and indicate a request to perform a recalibration of the PHY circuitry, wherein the second device further comprises recalibration circuitry to perform the recalibration based on the value written to the particular bit.
19. The system of claim 18 , wherein the set of control and status signals comprise a second set of control and status signals, the first device comprises a controller message bus register, bits of the controller message bus register are mapped to a first set of control and status signals, a particular bit of the controller message bus register is mapped to a PHY-initiated recalibration request signal, and another bit of the controller message bus register is mapped to a recalibration complete signal.
20. The system of claim 18 , wherein the interface comprises a PHY Interface for PCI Express, SATA, DisplayPort, and Converged IO Architectures.
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June 19, 2019
July 14, 2020
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