Disclosed are methods, systems and devices for operation of correlated electron switch (CES) devices. In one aspect, a CES device may be placed in any one of multiple impedance states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. In one implementation, a CES device may be placed in a high impedance or insulative state, or two more distinguishable low impedance or conductive states.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit device comprising: one or more correlated electron switch (CES) elements; one or more first terminals configured to receive one or more first signals to control operations to transition the at least one of the one or more CES elements between a low impedance and/or conductive state and a high impedance and/or insulative state; one or more second terminals to comprise signal pins external to the integrated circuit device, the one or more second terminals to be configured to receive an externally applied signal, the externally applied signal to be at a first voltage level during a first operation to place the at least one of the one or more CES elements in the low impedance and/or conductive state, the externally applied signal to be at a second voltage level during a second operation to place the least one of the one or more CES elements in the high impedance and/or insulative state; and a circuit configured to limit a magnitude of a current in the at least one of the one or more CES elements during the first operation to place the at least one of the one or more CES elements in the low impedance and/or conductive state responsive to the externally applied signal at the first voltage level received at the one or more second terminals.
2. The integrated circuit device of claim 1 , wherein at least one of the one or more first signals to represent a value specifying a duration of application of programming signals to terminals of the at least one of the one or more CES elements during the operations to transition the at least one of the one or more CES elements between the low impedance and/or conductive state and the high impedance and/or insulative state.
3. The integrated circuit of claim 1 , wherein the integrated circuit is further configured to selectively determine a duration of application of a zero voltage across terminals of the at least one of the one or more CES elements for a transitions of the at least one of the one or more CES elements between the low impedance and/or conductive state and the high impedance and/or insulative state based, at least in part, on at least one of the one or more first signals.
4. The integrated circuit of claim 3 , wherein the integrated circuit is further configured to determine the duration based, at least in part, on a digital signal mapped to alternative durations.
5. The integrated circuit device of claim 1 , the circuit configured to limit current in the at least one of the one or more CES elements to comprise multiple signal paths to a terminal of the at least one of the CES elements, wherein the integrated circuit is further configured to open at least one of the multiple signal paths during operations to place the at least one of the CES elements in the low impedance or conductive state.
6. The integrated circuit device of claim 1 , wherein the circuit configured to limit the magnitude of the current in the at least one of the one or more CES elements to comprise a conductive element to limit the magnitude of the current in the at least one of the one or more CES elements in operations to place the at least one of the one or more CES elements in the low impedance and/or conductive state responsive at least in part to a voltage applied to a terminal of the conductive element.
7. The integrated circuit device of claim 6 , wherein the conducive element to comprise a field effect transistor, and wherein the current in the at least one of the one or more CES elements to be adjustable responsive to adjustment of a voltage applied to a gate terminal of the field effect transistor.
8. The integrated circuit device of claim 1 , wherein the operations to transition the at least one of the one or more CES elements between the low impedance and/or conductive state and the high impedance and/or insulative state to occur on alternating cycles.
9. The integrated circuit device of claim 8 , wherein the one or more first signals to control a periodicity of the alternating cycles.
10. The integrated circuit device of claim 9 , and further comprising a circuit configured to vary the periodicity of the alternating cycles based, at least in part, on the one or more first signals.
11. The integrated circuit device of claim 10 , wherein the circuit configured to vary the periodicity of the alternating cycles is further configured to vary the periodicity of the alternating cycles according to a multi-bit code mapped to alternative periodicities of the alternating cycles.
12. A method comprising: applying one or more first signals to one or more first terminals of an integrated circuit device to control operations to transition at least one of one or more CES elements of the integrated circuit device between a low impedance and/or conductive state and a high impedance and/or insulative state; externally applying one or more second signals to one or more second terminals of the integrated circuit device during the operations to transition the at least one of one or more CES elements of the integrated circuit device between the low impedance and/or conductive state and the high impedance and/or insulative state, at least one of the one or more second signals to be at a first voltage level to place the at least one of the one or more CES elements in the low impedance and/or conductive state and to be at a second voltage level to place the at least one of the one or more CES elements in the high impedance and/or insulative state; and limiting a magnitude of a current in the at least one of the one or more CES elements in operations to place the at least one of the one or more CES elements in the low impedance and/or conductive state responsive to application of the at least one of the second signals to the one or more second terminals being at the first voltage level, the one or more second terminals comprising one or more signal pins external to the integrated circuit device.
13. The method of claim 12 , and further comprising measuring a difference between an impedance of the at least one of one or more CES elements in the high impedance and/or insulative state and the low impedance and/or conductive state based, at least in part, on signals on one or more third terminals of the integrated circuit device.
14. The method of claim 12 , and further comprising determining a duration of application of programming signals to terminals of the at least one of the one or more CES elements during the operations to transition the at least one of the one or more CES elements between the low impedance and/or conductive state and the high impedance and/or insulative state based, at least in part, on a signal representing a value specifying the duration.
15. The method of claim 12 , and further comprising selectively determining a duration of application of a zero voltage across terminals of the at least one of the one or more CES elements for transitions of the at least one of the one or more CES elements between the low impedance and/or conductive state and the high impedance and/or insulative state based, at least in part, on at least one of the one or more first signals.
16. The method of claim 15 , and further comprising controlling the duration based, at least in part, on a digital signal mapped to alternative durations.
17. The method of claim 12 , wherein limiting the magnitude of the current in the at least one of the one or more CES elements in operations to place the at least one of the one or more CES elements in the low impedance and/or conductive state comprises opening at least one signal path of multiple signal paths to a terminal of the at least one of the one or more CES elements.
18. The method of claim 12 , wherein limiting the magnitude of the current in the at least one of the one or more CES elements in operations to place the at least one of the one or more CES elements in the low impedance and/or conductive state to comprise adjusting a voltage applied to a gate terminal of a field effect transistor coupled between a terminal of the at least one of the one or more CES elements and a node.
19. The method of claim 12 , wherein the operations to transition the at least one of the one or more CES elements between the low impedance and/or conductive state and the high impedance and/or insulative state to occur on alternating cycles.
20. The method of claim 19 , the method further comprising controlling a periodicity of the alternating cycles based, at least in part, on the one or more first signals.
21. The method of claim 20 , and further comprising varying the periodicity of the alternating cycles based, at least in part, on the one or more first signals.
22. The method of claim 21 , and further comprising varying the periodicity of the alternating cycles according to a multi-bit code mapped to alternative periodicities of the alternating cycles.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 10, 2017
July 14, 2020
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