A method for generating FPGA-based prototype systems capable of implementing UFS HS-G4 communication protocols using inexpensive/slow FPGAs. ASIC/SoC-targeted circuit designs are modified to include a speed converter that causes a UFS controller to generate transmitted data streams at one-half operating speed (e.g., 146 MHz) during HS-G4 operations, modifies the transmitted data streams to intersperse filler data values between transmitted data values, and transmits the modified data streams to M-PHY physical interconnect devices (PIDs) at full speed (e.g., 292 MHz). The speed converter also receives full-speed HS-G4 data streams that include both data and filler values and causes the UFS controller to operate at one-half operating speed (e.g., 146 MHz) such that only data values are read. PLD-based prototype systems that include separate M-PHY PIDs mounted on PCBs are efficiently configured to implement the modified circuit design. A prototyping tool automatically incorporates the speed converters into submitted ASIC/SoC-targeted circuit designs.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for prototyping a circuit design including a controller and a physical interconnect layer connected by a standard interface bus and configured to communicate with an external device using a high-speed transmission frequency, the method comprising: generating a modified circuit design including a speed converter disposed in the standard interface bus, wherein the speed converter is configured to convert a first data stream including data values transmitted at a first frequency into a second data stream including both said data values and one or more filler values transmitted at a second frequency, wherein the first frequency is lower than the second frequency; and generating a physical prototype system that implements the modified circuit design, said physical prototype system including at least one programmable logic device (PLD) and a physical interconnect device operably connected by an interconnect structure that forms at least a portion of said standard interface bus, wherein said at least one PLD is configured to implement said controller and said physical interconnect device is configured to implement said physical interconnect layer, and wherein said second frequency of said second data stream facilitates re-transmission of said data values and said one or more filler values from said physical interconnect device at said high-speed transmission frequency.
2. The method of claim 1 , wherein generating said modified circuit design comprises implementing the standard interface bus using a first bus portion and a second bus portion such that the speed converter is coupled to the controller by said first bus portion and the speed converter is coupled to the physical interconnect layer by said second bus portion, whereby the speed converter receives the first data stream from the controller via the first bus portion and transmits the second data stream to the physical interconnect layer via the second bus portion.
3. The method of claim 2 , wherein generating said modified circuit design comprises configuring the speed converter to receive a third data stream including both data values and filler values from the physical interconnect layer via the second bus portion, and to transmit a fourth data stream to the controller via the first bus portion such that the controller receives only said data values transmitted in said third data stream at said first frequency.
4. The method of claim 3 , wherein the circuit design is defined such that the physical interconnect layer is implemented using a standard MIPI M-PHY layer configured to communicate with said external device using a High-Speed Gear 4 (HS-G4) transmission having said high-speed transmission frequency of approximately 11.6 Gbps, the standard interface bus is implemented using a standard 40-bit RMMI bus, and the controller is implemented using a UFS controller configured to transmit data and receive data on each line of said 40-bit RMMI bus at said second frequency equal to approximately 292 MHz during said HS-G4 data transmissions, and wherein generating said modified circuit design comprises configuring said speed converter such that said first frequency of said fourth data stream is equal to approximately 146 MHz.
5. The method of claim 3 , wherein generating the physical prototype system further comprises configuring said at least one PLD to implement said speed converter, the first bus portion and part of the second bus portion.
6. The method of claim 3 , wherein generating said modified circuit design comprises configuring said speed converter to modify a symbol clock signal received from the physical interconnect layer and to pass said modified symbol clock signal to said controller during a high-speed transmission operation, and to pass said symbol clock signal without modification to said controller during a low-speed transmission operation, and wherein the circuit design is defined such that the controller transmits said first data stream during said high-speed transmission operation in accordance with said modified symbol clock signal, and generates a fifth data stream including data values transmitted at a third frequency during said low-speed transmission operation in accordance with said unmodified symbol clock signal, said third frequency being lower than said second frequency.
7. The method of claim 6 , wherein the circuit design is defined such that the controller asserts a high-speed transmission signal during each said high-speed transmission operation, and de-asserts said high-speed transmission signal during each said low-speed transmission operation, and wherein generating said modified circuit design comprises configuring said speed converter to distinguish between said high-speed and said low-speed transmission operations based on said assertion/de-assertion of said high-speed transmission signal.
8. The method of claim 3 , wherein generating said modified circuit design comprises: configuring said speed converter to modify a symbol clock signal received from the physical interconnect layer and to pass said modified symbol clock signal to said controller during a high-speed reception operation, and to pass said symbol clock signal without modification to said controller during a low-speed transmission operation, further configuring said speed converter such that said fourth data stream is identical to said third data stream, and wherein the circuit design is defined such that the controller only captures said data values from said fourth data stream during said high-speed transmission operation in accordance with said modified symbol clock signal.
9. A prototype system for prototyping a circuit design including a Universal Flash Storage (UFS) controller and a M-PHY interconnect layer connected by a standard Reference M-PHY Module Interface (RMMI) bus and configured to communicate with an external device using a High-Speed Gear 4 (HS-G4) transmission frequency, the prototyping system comprising: at least one programmable logic device (PLD) configured to implement said UFS controller; an M-PHY physical interconnect device (PID) configured to implement said M-PHY interconnect layer; an interconnect structure operably connected between said PLD and said M-PHY PID and being operably configured to implement at least a portion of said standard RMMI interface bus; and a speed converter module disposed operably connected in the standard RMMI interface bus such that the speed converter module is coupled to the UFS controller by a first RMMI interface bus portion and to the M-PHY interconnect layer by a second RMMI interface bus portion, wherein the speed converter is configured to convert a first data stream received from the UFS controller via the first RMMI interface bus portion into a second data stream that is transmitted to the M-PHY interconnect layer via the second RMMI interface bus portion, wherein said first data stream includes data values transmitted at a first frequency, and wherein said second data stream includes both said data values and one or more filler values transmitted at a second frequency that is greater than the first frequency.
10. A prototyping tool implemented on a computer and utilized to prototype a circuit design including a controller and a physical interconnect layer connected by a standard interface bus and configured to communicate with an external device using a high-speed transmission frequency, the prototyping tool being configured to generate a modified circuit design including a speed converter disposed in the standard interface bus such that the speed converter is coupled to the controller by a first bus portion and to the physical interconnect layer by a second bus portion, wherein the speed converter is configured to convert a first data stream including data values that are received from the controller via the first bus portion at a first frequency into a second data stream including both said data values and one or more filler values that are transmitted to the physical interconnect layer via the second bus portion at a second frequency, wherein the first frequency is less than the second frequency, and wherein said second frequency of said second data stream facilitates re-transmission of said data values and said one or more filler values from said physical interconnect device at said high-speed transmission frequency.
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June 7, 2019
July 21, 2020
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