A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A write assist circuit, comprising: a control circuit configured to receive first and second memory row address information associated with one or more memory write operations for one or more memory cells, wherein the first and second memory row address information denotes row location of the one or more memory cells; and a voltage generator configured to provide a reference voltage to one or more bitlines coupled to the one or more memory cells, wherein the voltage generator comprises: a first capacitive element; and a second capacitive element, wherein during the memory write operation: based on the first memory row address information, the first capacitive element is configured to couple the reference voltage to a first negative voltage; and based on the second memory row address information, the first and second capacitive elements are configured to couple the reference voltage to a second negative voltage lower than the first negative voltage.
2. The write assist circuit of claim 1 , wherein the voltage generator further comprises a pull-down transistor configured to initialize the reference voltage to ground.
3. The write assist circuit of claim 2 , wherein the first capacitive element is configured to couple the reference voltage to the first negative voltage after the pull-down transistor is deactivated.
4. The write assist circuit of claim 2 , wherein the first and second capacitive elements are configured to couple the reference voltage to the second negative voltage after the pull-down transistor is deactivated.
5. The write assist circuit of claim 1 , wherein each of the first and second capacitive elements comprises a top capacitor plate coupled to a voltage potential and a bottom capacitor plate coupled to a circuit node associated with the reference voltage, and wherein the control circuit is configured to transition the voltage potential from a first value to a lower second value to couple the reference voltage to the second negative voltage.
6. The write assist circuit of claim 5 , wherein the control circuit is configured to transition the voltage potential coupled to the top capacitor plate of the first and second capacitive elements based on the first and second memory row address information.
7. A memory device, comprising: an array of memory cells; a write driver circuit configured to provide a reference voltage for memory write operations performed on one or more memory cells in the array of memory cells; and a write assist circuit configured to provide the reference voltage to the write driver circuit, wherein the write assist circuit comprises: a control circuit configured to receive first and second memory row address information associated with the memory write operations performed on the one or more memory cells in the array of memory cells, wherein the first and second memory row address information denotes row location of the one or more memory cells in the array of memory cells; and a voltage generator comprising: a first capacitive element; and a second capacitive element, wherein during the memory write operation: based on the first memory row address information, the first capacitive element is configured to couple the reference voltage to a first negative voltage; and based on the second memory row address information, the first and second capacitive elements are configured to couple the reference voltage to a second negative voltage lower than the first negative voltage.
8. The memory device of claim 7 , wherein each of the memory cells in the array of memory cells comprises a static random access memory cell.
9. The memory device of claim 7 , wherein the first and second memory row address information comprise row location of a memory cell in the array of memory cells subject to the memory write operation, and wherein the row location is associated with a first portion of the array of memory cells or a second portion of the array of memory cells positioned between the first portion of the array of memory cells and the write assist circuit.
10. The memory device of claim 9 , wherein in response to the row location being in the second portion of the array of memory cells, the first capacitive element is configured to couple the reference voltage to the first negative voltage.
11. The memory device of claim 9 , wherein in response to the row location being in the first portion of the array of memory cells, the first and second capacitive elements are configured to couple the reference voltage to the second negative voltage.
12. The memory device of claim 7 , wherein the voltage generator further comprises a pull-down transistor configured to initialize the reference voltage to ground.
13. The memory device of claim 12 , wherein the first capacitive element is configured to couple the reference voltage to the first negative voltage after the pull-down transistor is deactivated.
14. The memory device of claim 12 , wherein the first and second capacitive elements are configured to couple the reference voltage to the second negative voltage after the pull-down transistor is deactivated.
15. The memory device of claim 7 , wherein each of the first and second capacitive element comprises a top capacitor plate coupled to a voltage potential and a bottom capacitor plate coupled to a circuit node associated with the reference voltage, and wherein the control circuit is configured to transition the voltage potential from a first value to a lower second value to couple the reference voltage to the second negative voltage.
16. A method for memory write operations, comprising: receiving first and second memory row address information associated with the memory write operations for one or more memory cells, wherein the first and second memory row address information denotes row location of the one or more memory cells; providing a reference voltage to one or more bitlines coupled to the one or more memory cells; coupling, with a first capacitive element, the reference voltage to a first negative voltage based on the first memory row address information; and coupling, with the first capacitive element and a second capacitive element, the reference voltage to a second negative voltage lower than the first negative voltage based on the second memory row address information.
17. The method of claim 16 , wherein the providing the reference voltage comprises initializing, with a pull-down transistor, the reference voltage to ground prior to coupling the reference voltage to the first and second negative voltages.
18. The method of claim 17 , wherein the coupling the reference voltage to the first negative voltage comprises coupling the reference voltage to the first negative voltage after the pull-down transistor is deactivated.
19. The method of claim of claim 16 , wherein each of the first and second capacitive elements comprises a top capacitor plate coupled to a voltage potential and a bottom capacitor plate coupled to a circuit node associated with the reference voltage, and wherein the coupling the reference voltage to the second negative voltage comprises transitioning the voltage potential from a first value to a lower second value to couple the reference voltage to the second negative voltage.
20. The write assist circuit of claim 1 , wherein: the control circuit is configured to receive the first and second memory row address information associated with the one or more memory write operations for the one or more memory cells by a row signal line; and the second capacitive element is electrically connected to the row signal line.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 1, 2017
August 4, 2020
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