Embodiments of the present invention relate to a solution for supplying power to a processor. In some embodiments, there is provided a method for supplying power to a processor. The method comprises, in response to determining that an output voltage of a main power supply supplying power to a processor is lower than a predefined threshold, enabling an additional power supply to supply power to the processor. The method further comprises determining output power of the additional power supply. In addition, the method further comprises, in response to determining that the output power of the additional power supply exceeds peak power limit of the additional power supply, sending, by the additional power supply, a signal to the processor to lower a clock frequency of the processor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for supplying power to a processor, comprising: in response to determining that an output voltage of a main power supply supplying power to a processor is lower than a predefined threshold, enabling, by a control unit, an additional power supply to supply power to the processor, the control unit being located in the additional power supply; determining, by the control unit of the additional power supply, an output power of the additional power supply; and in response to determining that the output power of the additional power supply exceeds peak power limit of the additional power supply, sending, by the control unit of the additional power supply, a signal to the processor to lower a clock frequency of the processor.
2. The method according to claim 1 , further comprising: in response to determining that the output voltage of the main power supply is above the predefined threshold, disabling the additional power supply from supplying power to the processor.
3. The method according to claim 1 , wherein the determining output power of the additional power supply comprises: determining the output power of the additional power supply by detecting an output current of the additional power supply.
4. The method according to claim 1 , further comprising: in response to determining that the output power of the additional power supply is below the peak power limit of the additional power supply, ceasing sending the signal to the processor to restore the clock frequency of the processor.
5. The method according to claim 1 , further comprising: prior to enabling the additional power supply and in response to the output voltage of the main power supply being above the predefined threshold indicating that the main power supply is in a normal operating state, disabling the additional power supply from supplying power to the processor.
6. The method according to claim 1 , wherein the additional power supply includes a battery device; and wherein the method further comprises: charging the battery device of the additional power supply while the output voltage of the main power supply is above the predefined threshold.
7. The method according to claim 6 , wherein the main power supply is susceptible to a power loss event; and wherein the method further comprises: encountering a power loss event in which the output voltage of the main power supply drops below the predefined threshold, the battery device providing power to the processor during the power loss event.
8. The method according to claim 1 , further comprising: detecting, by circuitry of the additional power supply, whether the output voltage of the main power supply is below the predefined threshold, the additional power supply being disabled from supplying power to the processor while the output voltage of the main power supply is above the predefined threshold.
9. The method according to claim 8 wherein the main power supply provides a first clock frequency control signal to control the clock frequency of the processor; and wherein sending the signal to the processor to lower the clock frequency of the processor includes: providing, from the circuitry of the additional power supply, a second clock frequency control signal to control the clock frequency of the processor, the second clock frequency control signal being independent of the first clock frequency control signal.
10. The method according to claim 9 wherein providing, from the circuitry of the additional power supply, the second clock frequency control signal to control the clock frequency of the processor includes: outputting the second clock frequency control signal from the circuitry of the additional power supply to the processor, the second clock frequency control signal dropping overall power consumption from a first range in which the processor is susceptible to a data unusable and data loss (DUDL) event to a second range which protects the processor against a DUDL event.
11. The method according to claim 1 , wherein the additional power supply includes active throttling circuitry constructed and arranged to output a clock frequency control signal; and wherein sending the signal to the processor includes: when the power drawn from the additional power supply exceeds the peak power limit, outputting the clock frequency control signal from the active throttling circuitry of the additional power supply to the processor to lower the clock frequency of the processor.
12. The method according to claim 1 , wherein the main power supply and the additional power supply are constructed and arranged to deliver power to the processor via a mother board voltage regulator; and wherein the additional power supply is a battery on bus (BoB) coupled with active throttling circuitry.
13. An apparatus for controlling power supply to a processor, comprising: a control unit including a control module, a power determining module, and a signal sending module, wherein the control module of the control unit is configured to, in response to determining that an output voltage of a main power supply supplying power to a processor is lower than a predefined threshold, enable an additional power supply to supply power to the processor; wherein the power determining module of the control unit is configured to determine output power of the additional power supply; wherein the signal sending module of the control unit is configured to, in response to determining that the output power of the additional power supply exceeds peak power limit of the additional power supply, send a signal to the processor to lower a clock frequency of the processor, and wherein the control unit is located in the additional power supply.
14. The apparatus according to claim 13 , wherein the control module is further configured to: in response to determining that the output voltage of the main power supply is above the predefined threshold, disable the additional power supply from supplying power to the processor.
15. The apparatus according to claim 13 , wherein the power determining module is further configured to: determine the output power of the additional power supply by detecting an output current of the additional power supply.
16. The apparatus according to claim 13 , wherein the signal sending module is further configured to: in response to determining that the output power of the additional power supply is below the peak power limit of the additional power supply, cease sending the signal to the processor to restore the clock frequency of the processor.
17. The apparatus according to claim 13 , wherein the signal is sent via a reserved pin of the apparatus.
18. A power supply system, comprising: a processor; a main power supply for supplying power to the processor, the main power supply being configured to: in response to determining that first output power of the main power supply exceeds first peak power limit of the main power supply, send a first signal to the processor to lower a clock frequency of the processor; an additional power supply; and a control unit configured to: in response to determining that an output voltage of the main power supply is lower than a predefined threshold, enable the additional power supply to supply power to the processor; determine second output power of the additional power supply; and in response to determining that second output power of the additional power supply exceeds second peak power limit of the additional power supply, send, a second signal to the processor to lower the clock frequency of the processor, wherein the control unit is located in the additional power supply.
19. The power supply system according to claim 18 , further comprising a logic circuit via which the first and second signals are sent to the processor.
20. The power supply system according to claim 19 , wherein if both the first and second signals are active low, the logic circuit is an AND gate.
21. The power supply system according to claim 19 , wherein if both the first and second signals are active high, the logic circuit is an OR gate.
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June 14, 2017
August 11, 2020
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