A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A multi-processor computer system comprising: N processor cards, each of said processor cards being affixed in an array and including a process to generate memory requests having a memory address and a source identifier; and M multi-ported common memory modules allocated with an address range configured to be accessed by any of the N processor cards based on the memory requests, each of said multi-ported common memory modules being affixed in an array, wherein each M multi-ported common memory modules include a controller and a plurality of memory storage devices accessible by the controller, each controller including a processor port and a memory module port; said N processor cards and said M multi-ported common memory modules being toroidally interconnected such that the processor port for each M multi-ported common memory module is connected to one of said N processor cards such that the controller receives memory requests and executes said memory requests with respect to the plurality of storage devices if the memory address is within the address range associated with the controller and said memory module port for each M multi-ported common memory module is connected to relay memory requests to one of said M multi-ported common memory modules if the memory address is not within the address range associated with the controller, and wherein N is an integer greater than 1.
2. The multi-processor computer system of claim 1 further comprising: an additional N processor cards, each of said additional processor cards being affixed in the array, said additional N processor cards being toroidally interconnected to said M multi-ported common memory modules.
3. The multi-processor computer system of claim 1 wherein N≥3.
4. The multi-processor computer system of claim 1 wherein each of said M multi-ported common memory modules comprises four ports.
5. The multi-processor computer system of claim 1 wherein said controller comprises at least one of an FPGA, ASIC, CPLD, PLD, CSSP or PSoC.
6. The multi-processor computer system of claim 1 wherein said at least one memory storage device comprises a memory array comprising at least one SDRAM device.
7. The multi-processor computer system of claim 1 wherein said at least one memory storage device comprises Flash memory or a disk drive.
8. The multi-processor computer system of claim 1 wherein said arrays of processor card slots and memory module card slots comprises a portion of either a baseboard or backplane.
9. A method for processing data requests from an array comprising a plurality of interconnected processors and memory controllers, said method comprising: directing a data request having a memory address and a source identifier to a first port of a first one of said plurality of memory controllers from a first of the plurality of interconnected processors; if said memory address resides within an address range associated with said first one of said plurality of memory controllers: servicing said data request with the first one of said plurality of memory controllers by accessing a first memory storage device associated with the memory address; and returning said data requested within the address range to said first of the plurality of interconnected processors using the first port of said first one of said plurality of memory controllers based on the source identifier; otherwise: directing said data request to a second adjacent one of said plurality of memory controllers using a second port of said first one of said plurality of memory controllers; servicing said data request with said second adjacent one of said plurality of memory controllers by accessing a second memory storage device associated with the memory address; returning said data requested using said second adjacent one of said plurality of memory controllers to said second port of said first one of said plurality of memory modules; and returning said data requested using said first port of said first one of said plurality of memory controllers to said first of the plurality of interconnected processors based on the source identifier, wherein said plurality of interconnected processors are configured to access the first memory storage device and the second memory storage device based on the data request.
10. The method of claim 9 wherein said plurality of processors and memory controllers are toroidally interconnected.
11. The method of claim 9 wherein each of said plurality of processors and memory controllers are located on respective cards for insertion into corresponding card slots in a backplane.
12. The method of claim 9 wherein each of said plurality of processors and memory controllers are located on respective cards for insertion into corresponding card slots in a baseboard.
13. A multi-processor computer system comprising: a plurality of processor blocks, each block generating memory address requests having a memory address and a source identifier; and a multiplicity of multi-ported common memory modules allocated with an address range configured to be accessed by any of the plurality of processor blocks based on the memory address requests, each multi-ported common memory module having a controller and a plurality of memory storage devices, a processor port of the controller of each of said memory modules being associated with a corresponding one of said processor blocks, said memory modules being operational to relay memory access requests from a first one of said processor blocks directed to a corresponding first one of said memory modules to another one of said multiplicity of memory modules using a memory module port if a requested memory location is not found on said first one of said memory modules and returning accessed data using the processor port.
14. The multi-processor computer system of claim 13 wherein said another one of said multiplicity of memory modules is adjacent said first one of said memory modules.
15. The multi-processor computer system of claim 13 wherein said plurality of processor blocks and said multiplicity of multi-ported common memory modules are toroidally interconnected.
16. The multi-processor computer system of claim 13 wherein a control function of each of said multiplicity of multi-ported common memory modules is carried out by at least one of an FPGA, ASIC, CPLD, PLD, CSSP or PSoC.
17. The multi-processor computer system of claim 13 wherein said plurality of processor blocks and said multiplicity of multi-ported common memory modules each comprise respective card form factors for retention in corresponding card slots in a backplane.
18. The multi-processor computer system of claim 13 wherein said plurality of processor blocks and said multiplicity of multi-ported common memory modules each comprise respective card form factors for retention in corresponding card slots in a baseboard.
19. The multi-processor computer system of claim 13 wherein said multiplicity of multi-ported common memory modules comprises a shared common memory system for said plurality of processor blocks.
20. The multi-processor computer system of claim 13 wherein said multiplicity of multi-ported common memory modules comprises a non-shared common memory system for said plurality of processor blocks.
21. The multi-processor computer system of claim 13 wherein each of said multi-ported common memory modules comprise at least one of semiconductor or disk-based data storage devices.
22. The multi-processor computer system of claim 13 wherein said multi-ported common memory modules are operational to perform at least one of returning: 2D data in transpose order; 2D sub-volumes out of a larger 2D set of data; 2D planes out of 3D volumes; or 3D sub-volumes out of a larger 3D volume.
23. The multi-processor computer system of claim 13 wherein said multi-ported common memory modules are operational to perform gather-scatter DMA operations comprising at least one of providing for read/write operations a list of addresses and constant or a list of addresses and lengths.
24. The multi-processor computer system of claim 13 wherein said multi-ported common memory modules are operational to perform linked list DMA operations comprising following a linked list set of addresses to a final set of data read.
25. The multi-processor computer system of claim 13 wherein said multi-ported common memory modules are operational to return records of unknown length.
26. The multi-processor computer system of claim 25 wherein said length of said return records is determined by reading the record at a given address.
27. The multi-processor computer system of claim 13 wherein said multi-ported common memory modules are operational to return an address where data is written.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 28, 2013
August 11, 2020
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