In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit for saving and restoring a state of a design block, comprising: a first set of memory cells coupled in a first scan chain, wherein the first set of memory cells has a first number of cells (N); a second set of memory cells coupled in a second scan chain, wherein the second set of memory cells has a second number of cells (M) that is less than the first number of cells, and wherein the first set of memory cells and the second set of memory cells are configured to, during an initialization action, receive a first set of data and to store, in a first order, a first portion of the first set of data in the first set of memory cells and a second portion of the first set of data in the second set of memory cells; a second memory coupled to the first and second sets of memory cells and configured so that: during a save state action, a second set of data is read from the first and second sets of memory cells and stored in the second memory in a second order wherein the second order includes repeated portions of the second set of data stored in a sequentially first subset of N mod M memory cells of the second set od memory cells; and during a restore state action, of the second set of data is read from the second memory and stored, in the first order, in the first and second sets of memory cells and the repeated portions are stored, in the first order, in corresponding ones of the second set of memory cells.
2. The circuit of claim 1 further comprising: a memory controller coupled to the first and second sets of memory cells and to the second memory; and a multiplexer coupled between the second set of memory cells and the memory controller.
3. The circuit of claim 2 , wherein the multiplexer includes: an output coupled to a first cell of the second set of memory cells arranged first in the second scan chain; a first input coupled to an output of the memory controller; and a second input coupled to a second cell of the second set of memory cells arranged last in the second scan chain.
4. The circuit of claim 3 , wherein the second set of memory cells includes a third cell that is an intermediate cell of the second scan chain and that is coupled to an input of the memory controller.
5. The circuit of claim 2 wherein the first set of memory cells is coupled to the memory controller without an intervening multiplexer.
6. A circuit, comprising: a memory controller that includes first and second inputs and first and second outputs; a first set of memory cells coupled in a first scan chain, wherein: the first set of memory cells has a first number of cells; the first set of memory cells includes a first cell coupled to the first output of the memory controller and a second cell coupled to the first input of the memory controller; and the first set of memory cells is configured to receive a propagation signal; a second set of memory cells coupled in a second scan chain, wherein: the second set of memory cells has a second number of cells that is less than the first number of cells; the second set of memory cells includes a third cell coupled to the second output of the memory controller and a fourth cell coupled to the second input of the memory controller; and a memory coupled to the memory controller; the memory controller configured to: during a save state action, provide the propagation signal to the first and second sets of memory cells a number of times equal to the first number cells, and cause the memory to store a set of data outputted from the first and second sets of memory cells in a received order, so that data stored in the second set of memory cells is repeated when stored in the memory; and during a restore state action, cause the memory to output the set of data in the received order, and cause the first and second sets of memory cells to store the set of data outputted by the memory in the received order.
7. The circuit of claim 6 , wherein the propagation signal is a clock.
8. The circuit of claim 6 , further comprising a multiplexer coupled between the third cell of the second set of memory cells and the second output of the memory controller.
9. A circuit that includes: a controller that includes a first input, a second input, a first output, and a second output; a first scan chain that includes a first number of memory cells coupled in series, wherein the first scan chain includes: a first cell arranged first in the first scan chain that is coupled to the first output of the controller; and a second cell arranged last in the first scan chain that is coupled to the first input of the controller; and a second scan chain that includes a second number of memory cells coupled in series, wherein the second number of memory cells is less than the first number of memory cells, and wherein the second scan chain includes: a third cell arranged first in the second scan chain that is coupled to the second output of the controller; a fourth cell arranged last in the second scan chain that is coupled to the third cell; and a fifth cell that is an intermediate cell in the second scan chain that is coupled to the second input of the controller.
10. The circuit of claim 9 further comprising a multiplexer coupled between the second output of the controller and the third cell of the second scan chain.
11. The circuit of claim 10 wherein the multiplexer includes: a first input coupled to the fourth cell of the second scan chain; a second input coupled to the second output of the controller; and an output coupled to the third cell.
12. The circuit of claim 9 , wherein the first cell of the first scan chain is coupled to the first output of the controller without an intervening multiplexer.
13. The circuit of claim 9 further comprising a memory coupled to the controller, wherein the controller is operable to: perform a save state action that includes: causing the first scan chain and the second scan chain to provide a set of scan data; and storing the set of scan data in the memory, wherein the set of scan data includes a repeated portion of a subset of data stored in the second scan chain; and perform a restore state action that includes: retrieving the set of scan data from the memory; and causing the first scan chain and the second scan chain to store the set of scan data.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 28, 2018
August 18, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.