Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic memory apparatus, comprising: a memory cell in electronic communication with a digit line and operable to store a plurality of logic states; a current generator coupled to the digit line and operable to charge the digit line to a voltage level; a latch operable to output a value of a time-varying signal based at least in part on the current generator charging the digit line to the voltage level; and a controller coupled to the latch and operable to identify a logic state of the memory cell based at least in part on the value of the time-varying signal received from the latch.
2. The electronic memory apparatus of claim 1 , further comprising: a sense component coupled to a node of the current generator different than the digit line, the sense component operable to detect a voltage present on the node, wherein the voltage is based at least in part on the voltage level of the digit line.
3. The electronic memory apparatus of claim 2 , wherein the latch is coupled to the sense component and is operable to output the value of the time-varying signal based at least in part on receiving a signal from the sense component.
4. The electronic memory apparatus of claim 2 , wherein: the sense component comprises an inverter.
5. The electronic memory apparatus of claim 1 , wherein the current generator is operable to apply a time-varying current to the digit line to charge the digit line to the voltage level, wherein the value of the time-varying signal output by the latch is based at least in part on applying the time-varying current.
6. An electronic memory apparatus of claim 1 , further comprising: a second latch coupled to the controller and operable to output a value of a second time-varying signal based at least in part on the current generator charging the digit line to the voltage level.
7. The electronic memory apparatus of claim 6 , wherein the controller is operable to identify the logic state of the memory cell based at least in part on the value of the time-varying signal received from the latch and the value of the second time-varying signal received from the second latch.
8. The electronic memory apparatus of claim 1 , wherein the controller is operable to bias the digit line prior to the digit line being charged by the current generator.
9. The electronic memory apparatus of claim 1 , wherein the controller is operable to identify a first bit of the logic state stored in the memory cell after a first duration and identify a second bit of the logic state stored in the memory cell after a second duration.
10. The electronic memory apparatus of claim 1 , wherein: the current generator comprises a cascode.
11. The electronic memory apparatus of claim 1 , wherein: the plurality of logic states comprises a plurality of stable states and a plurality of volatile states.
12. The electronic memory apparatus of claim 1 , wherein the memory cell is operable to be operated as one of: a volatile memory cell, a non-volatile memory cell, or a partly volatile and a partly non-volatile memory cell.
13. A method, comprising: charging, using a time-varying current as part of a read operation, a digit line coupled to a memory cell; identifying a first bit of a logic state of the memory cell based at least in part on a first duration for charging a voltage of the digit line to a first voltage level; and identifying a second bit of the logic state based at least in part on a second duration for charging the voltage of the digit line to a second voltage level.
14. The method of claim 13 , further comprising: initiating a timer based at least in part on performing the read operation on the memory cell, wherein the first duration or the second duration is determined based at least in part on an amount of time that elapses between initiating the timer and the digit line charging to the first voltage level.
15. The method of claim 13 , further comprising: determining that a third voltage level at a node different from the digit line satisfies a voltage threshold, wherein the first duration is based at least in part on the third voltage level satisfying the voltage threshold.
16. The method of claim 13 , further comprising: identifying a first value of a time-varying signal at or after a first time when the voltage charges to the first voltage level, wherein identifying the first bit of the logic state is based at least in part on the first value of the time-varying signal at or after the first time; and identifying a second value of the time-varying signal at or after a second time when the voltage charges to the second voltage level, wherein identifying the second bit of the logic state is based at least in part on the second value of the time-varying signal at or after the second time.
17. The method of claim 13 , further comprising: biasing the digit line prior to charging the digit line.
18. A method, comprising: charging, using a time-varying current as part of a read operation, a digit line coupled to a memory cell; determining a time that a voltage level associated with the digit line satisfies a threshold based at least in part on charging the digit line; identifying, at or after the time that the voltage level satisfies the threshold, a first value of a first time-varying signal and a second value of a second time-varying signal; and identifying a logic state of the memory cell based at least in part on the first value of the first time-varying signal and the second value of the second time-varying signal.
19. The method of claim 18 , further comprising: initiating the first time-varying signal and the second time-varying signal based at least in part on charging the digit line, wherein identifying the first value and the second value at or after the time is based at least in part on initiating the first time-varying signal and the second time-varying signal.
20. The method of claim 18 , further comprising: determining a second time that a second voltage level at a node different than the digit line satisfies a second threshold based at least in part on charging the digit line, wherein identifying the first value and the second value at or after the time is based at least in part on the second voltage level satisfying the second threshold.
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July 16, 2019
August 25, 2020
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