A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming interconnections between a silicon die and external leads of a silicon chip package comprising: forming a pre-mold onto a front assembly of the silicon chip package, wherein the silicon die is disposed on the front assembly; etching a trace pattern on the pre-mold, wherein the trace pattern is representative of the interconnections; plating rigid traces onto the trace pattern; and forming a mold around the pre-mold and the plated rigid traces.
2. The method of claim 1 , wherein the pre-mold is formed using a plastic material.
3. The method of claim 2 , wherein the pre-mold is formed using Ajinomoto build-up film.
4. The method of claim 1 , wherein the etching is performed using ablation process.
5. The method of claim 1 , wherein the etching is performed using laser ablation.
6. The method of claim 1 , wherein the etching is performed until lead fingers are exposed, the lead fingers connecting the silicon die to the external leads.
7. The method of claim 1 , wherein the plating comprises: exposing the trace pattern, soaking the front assembly in a plating solution, and depositing plating material onto the trace pattern.
8. The method of claim 7 , wherein the plating solution comprises electro conductive ions that include copper, silver and gold.
9. The method of claim 7 , further comprising applying a catalyst before the soaking in a plating solution.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 30, 2019
August 25, 2020
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