A semiconductor device 1 includes a first drain terminal 4, connected to a drain electrode of a first semiconductor chip, a first gate terminal 5, connected to a gate electrode of the first semiconductor chip, a second drain terminal 6, connected to a drain electrode of a second semiconductor chip, a second gate terminal 7, connected to a gate electrode of the second semiconductor chip, a common source terminal 8, connected to a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip, and a sealing resin 9, sealing the respective semiconductor chips and the respective terminals. The respective terminals have exposed surfaces (lower surfaces) 43, 53, 63, 73, and 83 substantially flush with an outer surface (lower surface) 9b of the sealing resin 9 and exposed from the outer surface 9b.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device in which a semiconductor chip is sealed with a sealing resin, comprising: a first corner portion, a second corner portion adjacent to the first corner portion, a third corner portion facing the first corner portion diagonally, a fourth corner portion opposed to the second corner portion diagonally, a first terminal disposed in the vicinity of the first corner portion for electrically connecting to the outside, a second terminal disposed in the vicinity of the second corner portion for electrically connecting to the outside, a third terminal disposed in the vicinity of the fourth corner portion for electrically connecting to the outside, and a fourth terminal disposed in the vicinity of the third corner portion for electrically connecting to the outside, wherein an area as seen in plan view of the first terminal and an area as seen in plan view of the second terminal are the same size, an area as seen in plan view of the third terminal and an area as seen in plan view of the fourth terminal are the same size, the area as seen in plan view of the third terminal is larger than the area as seen in plan view of the first terminal, no terminal exists between the first terminal and the third terminal in plan view, and no terminal exists between the second terminal and the fourth terminal in plan view.
2. The semiconductor device according to claim 1 , wherein the sealing resin has first and second side surfaces opposed to each other, the first terminal and the second terminal are exposed from one side surface of the first and second side surfaces, and the third terminal and the fourth terminal are exposed from the other side surface of the first and second side surfaces.
3. The semiconductor device according to claim 2 , wherein the sealing resin has third and fourth side surfaces opposed to each other, other than the first and third side surfaces, the first terminal and the third terminal are exposed from one side surface of third and fourth side surfaces, and the second terminal and the fourth terminal are exposed from the other side surface of the third and fourth surfaces.
4. The semiconductor device according to claim 3 , wherein the sealing resin has two opposing surfaces, and the first terminal, the second terminal, the third terminal, and the fourth terminal are exposed from one surface of the two surfaces.
5. The semiconductor device according to claim 4 , further comprising a fifth terminal between the first terminal and the second terminal for electrical connection to the outside, wherein the fifth terminal is exposed from the one side surface of the first and second side surfaces and is exposed from one surface of the two surfaces in the sealing resin.
6. The semiconductor device according to claim 2 , further comprising a fifth terminal between the first terminal and the second terminal for electrical connection to the outside, wherein the fifth terminal is exposed from the one side surface of the first and second side surfaces.
7. The semiconductor device according to claim 1 , further comprising a fifth terminal between the first terminal and the second terminal for electrical connection to the outside.
8. The semiconductor device according to claim 7 , wherein an area as seen in plan view of the fifth terminal is larger than the area as seen in plan view of the first terminal and smaller than the area as seen in plan view of the third terminal.
9. The semiconductor device according to claim 7 , wherein the semiconductor chip includes a first semiconductor chip and a second semiconductor chip, the first semiconductor chip is electrically connected to the first terminal and the third terminal, the second semiconductor chip is electrically connected to the second terminal and the fourth terminal, the first semiconductor chip and the second semiconductor chip are each electrically connected to the fifth terminal.
10. The semiconductor device according to claim 9 , wherein the first terminal is a first gate terminal for connecting the gate electrode of the first semiconductor chip, the third terminal is a first drain terminal for connecting a drain electrode of the first semiconductor chip, the second terminal is a second gate terminal for connecting a gate electrode of the second semiconductor chip, the fourth terminal is a second drain terminal for connecting a drain electrode of the second semiconductor chip, and the fifth terminal is a source terminal for connecting a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip.
11. The semiconductor device according to claim 10 , wherein the source electrode of the first semiconductor chip is connected to the fifth terminal via a first bonding wire, the gate electrode of the first semiconductor chip is connected to the first terminal via a second bonding wire, the drain electrode of the first semiconductor chip is directly connected to the third terminal, the source electrode of the second semiconductor chip is connected to the fifth terminal via a third bonding wire, the gate electrode of the second semiconductor chip is connected to the second terminal via a fourth bonding wire, and the drain electrode of the second semiconductor chip is directly connected to the fourth terminal.
12. The semiconductor device according to claim 11 , wherein each of the first terminal, the second terminal, the third terminal, the fourth terminal, and the fifth terminal has an exposed surface exposed on one surface of two surfaces of the sealing resin.
13. The semiconductor device according to claim 12 , wherein the one surface of the sealing resin has a first side and a second side that are mutually opposed, a third side joining one ends of the first side and the second side together, and a fourth side joining other ends of the first side and the second side together, the exposed surface of the first terminal is disposed at a first corner portion at which the first side and the third side of the one surface are joined, the exposed surface of the second terminal is disposed at a second corner portion at which the first side and the fourth side of the one surface are joined, the exposed surface of the third terminal is disposed at a third corner portion at which the second side and the third side of the one surface are joined, the exposed surface of the fourth terminal is disposed at a fourth corner portion at which the second side and the fourth side of the one surface are joined, and the exposed surface of the fifth terminal is disposed at an intermediate position of the one surface between the exposed surface of the first terminal and the exposed surface of the second terminal.
16. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a first semiconductor chip and a second semiconductor chip, the first semiconductor chip is electrically connected to the first terminal and the third terminal, and the second semiconductor chip is electrically connected to the second terminal and the fourth terminal.
17. The semiconductor device according to claim 16 , wherein a first surface side of the first semiconductor chip is connected to the first terminal, a second surface side of the first semiconductor chip opposite to the first surface side is connected to the third terminal, a first surface side of the second semiconductor chip is connected to the second terminal, and a second surface side of the second semiconductor chip opposite to the first surface side is connected to the fourth terminal.
18. The semiconductor device according to claim 16 , wherein the first terminal is a first gate terminal for connecting a gate electrode of the first semiconductor chip, the third terminal is a first drain terminal for connecting a drain electrode of the first semiconductor chip, the second terminal is a second gate terminal for connecting a gate electrode of the second semiconductor chip, and the fourth terminal is a second drain terminal for connecting a drain electrode of the second semiconductor chip.
19. The semiconductor device according to claim 18 , wherein the gate electrode of the first semiconductor chip is connected to the first terminal via a second bonding wire, the drain electrode of the first semiconductor chip is directly connected to the third terminal, the gate electrode of the second semiconductor chip is connected to the second terminal via a fourth bonding wire, and the drain electrode of the second semiconductor chip is directly connected to the fourth terminal.
20. The semiconductor device according to claim 1 , wherein an interval between the first terminal and the second terminal is larger than an interval between the third terminal and the fourth terminal in plan view.
21. The semiconductor device according to claim 1 , wherein no terminal exists between the third terminal and the fourth terminal in plan view.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 6, 2019
September 8, 2020
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