An analog-to-digital converter includes: a first to an (m+1)-th capacitive element each of which has a first end connected to a first terminal of a comparison circuit and have a predetermined capacitance ratio; and selection circuits which are connected to second ends of the capacitive elements, respectively. Each of the capacitive elements includes: a first electrode disposed in a semiconductor substrate and electrically connected to the second end; a third electrode disposed above the semiconductor substrate to oppose the first electrode and electrically connected to the second end; a second electrode disposed between the first electrode and the third electrode, above the semiconductor substrate, and electrically connected to the first end; a first insulation film disposed between the first and second electrodes; and a second insulation film disposed between the third and second electrodes.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A robot comprising: a base; and an arm that is supported to be movable with respect to the base and includes a solid- state imaging device, wherein the solid-state imaging device includes an analog-to-digital converter that performs analog-to-digital conversion on a pixel signal generated by reading pixel information from a light receiving element, the analog-to-digital converter includes: a comparison circuit that compares a voltage applied to a first terminal with a reference voltage applied to a second terminal, and outputs an output signal indicating a comparison result from a third terminal; capacitive elements each of which has a first end connected to the first terminal of the comparison circuit via a first line, and includes: a first to an m-th capacitive element (where m is an integer of 2 or more) that each have a predetermined capacitance ratio; and an (m+1)-th capacitive element that has a capacitance that is substantially same as the capacitance of the first capacitive element; and selection circuits that are connected to second ends of the capacitive elements, respectively, via second lines, and each of the capacitive elements includes: a first electrode disposed in a semiconductor substrate and electrically connected to the second end; a third electrode disposed above the semiconductor substrate to oppose the first electrode and electrically connected to the second end; a second electrode disposed between the first electrode and the third electrode, above the semiconductor substrate, to oppose the first electrode and the third electrode and electrically connected to the first end; a first insulation film disposed between the first electrode and the second electrode; a second insulation film disposed between the third electrode and the second electrode; wherein the capacitive elements are configured in a capacitive cell array that includes capacitive cells disposed in rows and columns to be symmetric with respect to a symmetry axis, and each of second to the m-th capacitive elements of the first to the m-th capacitive elements includes at least one capacitive cell disposed on one side of the symmetry axis, and the same number of capacitive cells as that disposed on the one side are disposed on the other side of the symmetry axis.
2. An analog-to-digital converter comprising: a comparison circuit that compares a voltage applied to a first terminal with a reference voltage applied to a second terminal, and outputs an output signal indicating a comparison result from a third terminal; capacitive elements each of which has a first end connected to the first terminal of the comparison circuit via a first line, and includes: a first to an m-th capacitive element (where m is an integer of 2 or more) that each have a predetermined capacitance ratio; and an (m+1) -th capacitive element that has a capacitance that is substantially same as the capacitance of the first capacitive element; and selection circuits that are connected to second ends of the capacitive elements, respectively, via second lines, wherein each of the capacitive elements includes: a first electrode disposed in a semiconductor substrate and electrically connected to the second end; a third electrode disposed above the semiconductor substrate to oppose the first electrode and electrically connected to the second end; a second electrode disposed between the first electrode and the third electrode, above the semiconductor substrate, to oppose the first electrode and the third electrode and electrically connected to the first end; a first insulation film disposed between the first electrode and the second electrode; a second insulation film disposed between the third electrode and the second electrode; wherein the capacitive elements are configured in a capacitive cell array that includes capacitive cells disposed in rows and columns to be symmetric with respect to a symmetry axis, and each of second to the m-th capacitive elements of the first to the m-th capacitive elements includes at least one capacitive cell disposed on one side of the symmetry axis, and the same number of capacitive cells as that disposed on the one side are disposed on the other side of the symmetry axis.
3. The analog-to-digital converter according to claim 2 , wherein the second lines are disposed in a layer higher than the first line.
4. The analog-to-digital converter according to claim 2 , wherein each of second to the m-th capacitive elements includes at least two capacitive cells disposed symmetrically with respect to the symmetry axis.
5. The analog-to-digital converter according to claim 2 , wherein the first capacitive element includes one capacitive cell and the (m+1)-th capacitive element includes one capacitive cell, the one capacitive cell of the first capacitive element and the one capacitive cell of the (m+1)-th capacitive element being disposed symmetrically with respect to the symmetry axis.
6. The analog-to-digital converter according to claim 2 , wherein the second lines are disposed symmetrically with respect to the symmetry axis in a predetermined wiring layer.
7. The analog-to-digital converter according to claim 2 , wherein, when an analog signal is converted into a digital signal, the first to the m-th capacitive elements are used to generate higher-order m bits of the digital signal through successive approximation A/D (analog-to-digital) conversion.
8. The analog-to-digital converter according to claim 7 , wherein, when the analog signal is converted into the digital signal, the (m+1)-th capacitive element is used to generate an m-th bit and a subsequent bit of the digital signal through integral A/D conversion, and the higher-order m bits of the digital signal generated through the successive approximation A/D conversion are added to the m-th bit and the subsequent bit of the digital signal generated through the integral A/D conversion.
9. An imaging device, comprising: a light receiving element that has a photoelectric conversion function; and the analog-to-digital converter according to claim 2 , the analog-to-digital converter performing analog-to-digital conversion on a pixel signal generated by reading pixel information from the light receiving element.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 27, 2018
September 8, 2020
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