An integrated circuit includes transistor devices, each having a back gate. A controller is connected to the back gate to apply voltages to the back gate, wherein a first mode includes a first voltage for operational threshold voltages for the transistor devices, and a second mode includes a second voltage that enhances threshold voltage variability of the plurality of transistor devices to provide a physically unclonable function (PUF) for chip identification.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit, comprising: a plurality of transistor devices each having a back gate that includes a region formed distinct from a body of each of the plurality of transistor devices; and a controller connected to the back gate to apply voltages to the back gate, wherein the controller includes a first mode that includes a first voltage for operational threshold voltages for the plurality of transistor devices and a second mode that includes a second voltage that enhances threshold voltage variability of the plurality of transistor devices to provide a physically unclonable function (PUF) for chip identification.
2. The circuit as recited in claim 1 , wherein the plurality of transistor devices includes field effect transistors having the back gate formed in a well of a semiconductor substrate.
3. The circuit as recited in claim 2 , wherein the semiconductor substrate includes a fully depleted semiconductor-on-insulator substrate.
4. The circuit as recited in claim 1 , wherein the circuit includes at least one ring oscillator.
5. The circuit as recited in claim 1 , wherein the plurality of transistor devices includes n-type field effect transistors (NFETs) and the second voltage includes a positive back gate bias.
6. The circuit as recited in claim 1 , wherein the plurality of transistor devices includes p-type field effect transistors (PFETs) and the second voltage includes a negative back gate bias.
7. The circuit as recited in claim 1 , wherein the PUF for chip authentication includes a threshold voltage variability pattern of the plurality of transistor devices.
8. The circuit as recited in claim 7 , wherein the PUF is employed by a computer system to authenticate an identity of the integrated circuit.
9. The circuit as recited in claim 1 , wherein the back gate is electrically isolated from a body of each of the plurality of transistor devices.
10. An integrated circuit, comprising: a fully depleted semiconductor-on-insulator substrate (FDSOI) having a back gate of field effect transistors that includes a region formed distinct from a body of each of the field effect transistors formed below a buried dielectric layer of the FDSOI substrate, the FDSOI substrate including a semiconductor layer forming source regions, channel regions and drain regions; a front gate structure formed on the semiconductor layer to form the field effect transistors; and a controller connected to the back gate to apply voltages to the back gate of the field effect transistors, wherein the controller includes a first mode that includes a first voltage for operational threshold voltages for the field effect transistors and a second mode that includes a second voltage that enhances threshold voltage variability of the field effect transistors to provide a physically unclonable function (PUF) for chip identification.
11. The circuit as recited in claim 10 , wherein the field effect transistors include the back gate formed in a well of a base semiconductor substrate.
12. The circuit as recited in claim 10 , wherein the circuit includes at least one ring oscillator.
13. The circuit as recited in claim 12 , wherein the circuit includes: at least two multiplexers configured to receive input from the at least one ring oscillator and to receive a challenge; and a response component to determine a response to the challenge for authentication of a chip including the circuit.
14. The circuit as recited in claim 10 , wherein the field effect transistors include n-type field effect transistors (NFETs) and the second voltage includes a positive back gate bias.
15. The circuit as recited in claim 10 , wherein the field effect transistors include p-type field effect transistors (PFETs) and the second voltage includes a negative back gate bias.
16. The circuit as recited in claim 10 , wherein the PUF for chip authentication includes a threshold voltage variability pattern of the field effect transistors.
17. The circuit as recited in claim 16 , wherein the PUF is employed by a computer system to authenticate an identity of the integrated circuit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 13, 2017
September 15, 2020
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