Computer architecture for emulating a binary correlithm object logic gate

1. A system for implementing a binary correlithm object logic function gate with immunity to significant voltage surges and other noise impulses including electromagnetic pulses (EMP), comprising: a device for emulating the binary correlithm object logic function gate, the device comprising: a memory operable to store a logical operator truth table, the truth table comprising: a first group of input logical values including a logical zero value represented by a first correlithm object and a logical one value represented by a second correlithm object; a second group of input logical values including the logical zero value represented by a third correlithm object and the logical one value represented by a fourth correlithm object; and a group of output logical values including the logical zero value represented by a fifth correlithm object and the logical one value represented by a sixth correlithm object; a logic engine communicatively coupled to the memory and configured to: receive a first input comprising a first digital bit representing the logical zero value, the logical one value or noise; represent the received first input by a seventh correlithm object; receive a second input comprising a second digital bit representing the logical zero value, the logical one value or noise; represent the received second input by an eighth correlithm object; determine the Hamming distance between the seventh correlithm object and the first correlithm object; determine the Hamming distance between the seventh correlithm object and the second correlithm object; determine that the Hamming distance between the seventh correlithm object and the first correlithm object is smaller than the Hamming distance between the seventh correlithm object and the second correlithm object; determine the Hamming distance between the eighth correlithm object and the third correlithm object; determine the Hamming distance between the eighth correlithm object and the fourth correlithm object; determine that the Hamming distance between the eighth correlithm object and the third correlithm object is smaller than the Hamming distance between the eighth correlithm object and the fourth correlithm object; determine one of the fifth correlithm object and the sixth correlithm object as an output based at least in part on the determination that the Hamming distance between the seventh correlithm object and the first correlithm object is smaller than the Hamming distance between the seventh correlithm object and the second correlithm object and the determination that the Hamming distance between the eighth correlithm object and the third correlithm object is smaller than the Hamming distance between the eighth correlithm object and the fourth correlithm object; wherein: the first correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the first correlithm object is modified in response to a noise event, the remaining bits accurately represent the logical zero value; the second correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the second correlithm object is modified in response to a noise event, the remaining bits accurately represent the logical one value; the third correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the third correlithm object is modified in response to a noise event, the remaining bits accurately represent the logical zero value; and the fourth correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the fourth correlithm object is modified in response to a noise event, the remaining bits accurately represent the logical one value; and implement the binary correlithm object logic function gate with immunity to significant voltage surges and other noise impulses including electromagnetic pulses (EMP) based on the results of the emulation.

2. The device of claim 1 , wherein determining that the Hamming distance between the seventh correlithm object and the first correlithm object is smaller than the Hamming distance between the seventh correlithm object and the second correlithm object indicates that the logical value represented by the seventh correlithm object is more similar to the logical value represented by the first correlithm object than the logical value represented by the second correlithm object even if the seventh correlithm object does not exactly match the first correlithm object.

3. The device of claim 1 , wherein the truth table implements a logical operator function and the determination of the fifth correlithm object and the sixth correlithm object as an output is further based upon the implemented logical operator function.

4. The device of claim 3 , wherein the truth table implements one of a plurality of logical operator functions selected by a context input correlithm object.

5. A system for implementing a binary correlithm object logic function gate with immunity to significant voltage surges and other noise impulses including electromagnetic pulses (EMP), comprising: a device for emulating the binary correlithm object logic function gate, the device comprising: a memory operable to store a logical operator truth table, the truth table comprising: a first group of input logical values including a first logical state value represented by a first correlithm object and a second logical state value represented by a second correlithm object; a second group of input logical values including the first logical state value represented by a third correlithm object and the second logical state value represented by a fourth correlithm object; and a group of output logical values including the first logical state value represented by a fifth correlithm object and the second logical state value represented by a sixth correlithm object; a logic engine communicatively coupled to the memory and configured to: receive a first input comprising a first digital bit representing the first logical state value, the second logical state value or noise; represent the received input by a seventh correlithm object; receive a second input comprising a second digital bit representing the first logical state value, the second logical state value or noise; represent the received second input by an eighth correlithm object; determine the distance in n-dimensional space between the seventh correlithm object and the first correlithm object; determine the distance in n-dimensional space between the seventh correlithm object and the second correlithm object; select one of the first correlithm object and the second correlithm object based on which has the smaller distance in n-dimensional space to the seventh correlithm object; determine the distance in n-dimensional space between the eighth correlithm object and the third correlithm object; determine the distance in n-dimensional space between the eighth correlithm object and the fourth correlithm object; select one of the third correlithm object and the fourth correlithm object based on which has the smaller distance in n-dimensional space to the eighth correlithm object; determine one of the fifth correlithm object and the sixth correlithm object as an output based on the selection of one of the first and second correlithm objects and the selection of one of the third and fourth correlithm objects; wherein: the first correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the first correlithm object is modified in response to a noise event, the remaining bits accurately represent the first logical state values; the second correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the second correlithm object is modified in response to a noise event, the remaining bits accurately represent the second logical state values; the third correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the third correlithm object is modified in response to a noise event, the remaining bits accurately represent the first logical state values; and the fourth correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the fourth correlithm object is modified in response to a noise event, the remaining bits accurately represent the second logical state values; and implement the binary correlithm object logic function gate with immunity to significant voltage surges and other noise impulses including electromagnetic pulses (EMP) based on the results of the emulation.

6. The device of claim 5 , wherein first logical state value comprises a logical zero value and the second logical state value comprises a logical one value.

7. The device of claim 5 , wherein: the distance in n-dimensional space between the seventh correlithm object and the first correlithm object indicates a similarity between the logical state value represented by the seventh correlithm object and the logical state value represented by the first correlithm object; and the distance in n-dimensional space between the seventh correlithm object and the second correlithm object indicates a similarity between the logical state value represented by the seventh correlithm object and the logical state value represented by the second correlithm object.

8. The device of claim 5 , wherein each of the determined distances in n-dimensional space is a Hamming distance.

9. The device of claim 5 , wherein: the first group of input logical values is arranged in a logical first row with ordered values 0, 0, 1, 1; and the second group of input logical values is arranged in a logical first row with ordered values 0, 1, 0, 1.

10. The device of claim 9 , wherein the truth table implements a logical operator selected from the group consisting of: a contradiction function with ordered values 0, 0, 0, 0; Not OR (NOR) function with ordered values 1, 0, 0, 0; Converse Non-implication function with ordered values 0, 1, 0, 0; Negation of a first input function with ordered values 1, 1, 0, 0; Material Non-implication function with ordered values 0, 0, 1, 0; Negation of a second input function with ordered values 1, 0, 1, 0; Exclusive OR (XOR) function with ordered values 0, 1, 1, 0; Not AND (NAND) function with ordered values 1, 1, 1, 0; AND function with ordered values 0, 0, 0, 1; Exclusive Not OR (XNOR) function with ordered values 1, 0, 0, 1; Projection of the first input function with ordered values 0, 0, 1, 1; if/then function with ordered values 1, 1, 0, 1; Projection of the second input function with ordered values 0, 1, 0, 1; then/if function with ordered values 1, 1, 0, 1; OR function with ordered values 0, 1, 1, 1; and Tautology function with ordered values 1, 1, 1, 1.

11. The device of claim 5 , wherein the truth table implements a logical operator function.

12. The device of claim 5 , wherein the truth table implements one of a plurality of logical operator functions selected by a context input correlithm object.

13. A method for implementing a binary correlithm object logic function gate with immunity to significant voltage surges and other noise impulses including electromagnetic pulses (EMP), comprising: emulating the binary correlithm object logic function gate, comprising: storing a logical operator truth table, the truth table comprising: a first group of input logical values including a first logical state value represented by a first correlithm object and a second logical state value represented by a second correlithm object; a second group of input logical values including the first logical state value represented by a third correlithm object and the second logical state value represented by a fourth correlithm object; and a group of output logical values including the first logical state value represented by a fifth correlithm object and the second logical state value represented by a sixth correlithm object; receiving a first input comprising a first digital bit representing the first logical state values, the second logical state values or noise; representing the received input by a seventh correlithm object; receiving a second input comprising a second digital bit representing the first logical state value, the second logical state value or noise; representing the received second input by an eighth correlithm object; determining the distance in n-dimensional space between the seventh correlithm object and the first correlithm object; determining the distance in n-dimensional space between the seventh correlithm object and the second correlithm object; selecting one of the first correlithm object and the second correlithm object based on which has the smaller distance in n-dimensional space to the seventh correlithm object; determining the distance in n-dimensional space between the eighth correlithm object and the third correlithm object; determining the distance in n-dimensional space between the eighth correlithm object and the fourth correlithm object; selecting one of the third correlithm object and the fourth correlithm object based on which has the smaller distance in n-dimensional space to the eighth correlithm object; and determining one of the fifth correlithm object and the sixth correlithm object as an output based on the selection of one of the first and second correlithm objects and the selection of one of the third and fourth correlithm objects; wherein: the first correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the first correlithm object is modified in response to a noise event, the remaining bits accurately represent the first logical state values; the second correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the second correlithm object is modified in response to a noise event, the remaining bits accurately represent the second logical state values; the third correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the third correlithm object is modified in response to a noise event, the remaining bits accurately represent the first logical state values; and the fourth correlithm object comprises an n-bit digital word of binary values such that if one of the bits of the fourth correlithm object is modified in response to a noise event, the remaining bits accurately represent the second logical state values; and implementing the binary correlithm object logic function gate with immunity to significant voltage surges and other noise impulses including electromagnetic pulses (EMP) based on the results of the emulation.

14. The method of claim 13 , wherein first logical state value comprises a logical zero value and the second logical state value comprises a logical one value.

15. The method of claim 13 , wherein: the distance in n-dimensional space between the seventh correlithm object and the first correlithm object indicates a similarity between the logical state value represented by the seventh correlithm object and the logical state value represented by the first correlithm object; and the distance in n-dimensional space between the seventh correlithm object and the second correlithm object indicates a similarity between the logical state value represented by the seventh correlithm object and the logical state value represented by the second correlithm object.

16. The method of claim 13 , wherein each of the determined distances in n-dimensional space is a Hamming distance.

17. The method of claim 13 , wherein: the first group of input logical values is arranged in a logical first row with ordered values 0, 0, 1, 1; and the second group of input logical values is arranged in a logical first row with ordered values 0, 1, 0, 1.

18. The method of claim 17 , further comprising using the truth table to implement a logical operator selected from the group consisting of: a contradiction function with ordered values 0, 0, 0, 0; Not OR (NOR) function with ordered values 1, 0, 0, 0; Converse Non-implication function with ordered values 0, 1, 0, 0; Negation of a first input function with ordered values 1, 1, 0, 0; Material Non-implication function with ordered values 0, 0, 1, 0; Negation of a second input function with ordered values 1, 0, 1, 0; Exclusive OR (XOR) function with ordered values 0, 1, 1, 0; Not AND (NAND) function with ordered values 1, 1, 1, 0; AND function with ordered values 0, 0, 0, 1; Exclusive Not OR (XNOR) function with ordered values 1, 0, 0, 1; Projection of the first input function with ordered values 0, 0, 1, 1; if/then function with ordered values 1, 1, 0, 1; Projection of the second input function with ordered values 0, 1, 0, 1; then/if function with ordered values 1, 1, 0, 1; OR function with ordered values 0, 1, 1, 1; and Tautology function with ordered values 1, 1, 1, 1.

19. The method of claim 13 , further comprising using the truth table to implement a logical operator function.

20. The method of claim 13 , further comprising using the truth table to implement one of a plurality of logical operator functions selected by a context input correlithm object.