A parallel processor comprising elementary processors disposed according to a topology with a predetermined position within this topology and capable of simultaneously executing the same instruction on different data, the instruction relating to at least one operand and/or providing at least one result The instruction comprises, for each operand and/or each result, information relating to the position of a field of action within a table data structure of dimension N type, and the parallel processor calculates the address of each operand and calculates the address of each result within each elementary processor, as a function of the position of the field of action and of the position of the elementary processor within the topology.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A parallel processor comprising: a number Np of elementary processors, Np≥2, each having a respective calculating unit and a respective memory, each said respective memory of the Np elementary processors including memory words, the Np elementary processors being disposed according to a P-dimensional topology, P≥1, with a predetermined position for each of the Np elementary processors, each of said Np elementary processors being configured to simultaneously execute a same instruction on different data of an N-dimensional data structure, N≥1, including elements, each element of said data structure being attributed to one elementary processor and to one address inside the attributed elementary processor, the instruction including reading at least one operand and/or writing at least one result; wherein the instruction, without providing an address for the at least one operand and/or an address for the at least one result within each said memory for each elementary processor to read or write, defines a position of a field of action in said data structure, the field of action being an Np sized data subset of said data structure, the data in the Np sized data subset being distributed according to the P dimension(s) of the P-dimensional topology; and wherein the parallel processor is further configured to calculate the address for the at least one operand and/or the address for the at least one result within each of said elementary processors to read or write, as a function of the position of the field of action and as a function of: said predetermined position of each elementary processor in the P-dimensional topology, and said number Np of the elementary processors, wherein the address for the at least one operand and/or the address for the at least one result within each of said elementary processors to read or write is obtained by a formula which contains an addition or subtraction of a value related to the position of the field of action and a value related to the predetermined position of each elementary processor.
2. The parallel processor as claimed in claim 1 , wherein the parallel processor is further configured for centrally calculating the position of the field of action for the at least one operand or for the at least one result and sharing the calculated position between the elementary processors.
3. The parallel processor as claimed in claim 1 , wherein the parallel processor is further configured for locally calculating said address for said at least one operand or said address for said at least one result at a level of each of said elementary processors.
4. The parallel processor as claimed in claim 1 , wherein the parallel processor is configured for partially grouping the calculation of said address for said at least one operand or said address for said at least one result between several elementary processors and partially locally carrying out the calculation of said address for said at least one operand or said address for said at least one result at a level of each of said elementary processors.
5. The parallel processor as claimed in claim 1 , wherein, for each given dimension of said P dimension(s), the parallel processor is configured to calculate an address of an element of the data structure which relates to one of the Np elementary processors, wherein said address of the element of the data structure is calculated by combining (i) a value related to the position of the field of action for the at least one operand or for the at least one result and (ii) a value related to a position p of the one of the Np elementary processors in said given dimension, p being an integer.
6. The parallel processor as claimed in claim 1 , wherein with the field of action for the at least one operand or for the at least one result having ends defined by respective coordinates and by respective positions of the ends in the topology, the position of the field of action for the at least one operand or for the at least one result is defined by a position of one of the ends whose coordinates are a minimum among the respective coordinates.
8. The parallel processor as claimed in claim 7 , wherein the topology has one dimension, the data structure is monodimensional, and the position of the field of action for the at least one operand or for the at least one result is defined as a minimum value (X min) of an X coordinate such that W min=X min.
9. The parallel processor as claimed in claim 8 , wherein Np is a power of 2, and the address (Ad) of an element of the data structure is calculated by steps: (1) adding X min and (Np−1−p), and (2) deleting the last LNp bits of a result of the adding in step (1), LNp being the base 2 logarithm of Np.
10. The parallel processor as claimed in claim 7 , wherein the elementary processors are disposed according to the topology having one dimension, and the data structure is bidimensional, said data structure being defined as a function of X and Y coordinates, and wherein the position of the field of action for the at least one operand or for the at least one result is defined by X min and Y min, where W min=X min+Lx*Y min, and X min and Y min are minimum values of the X and the Y coordinates of elements of the field of action, Lx being a width of the bidimensional data structure along an X dimension, and W min being defined on said one dimension as a function of the X and the Y coordinates of said position of the field of action.
11. The parallel processor as claimed in claim 10 , wherein when Np and Lx are powers of 2, an address Ad of an element of the data structure is calculated by steps: (1) adding X min and (Np−1−p), (2) deleting the last LNp bits of a result of the adding in step (1), LNp being the base 2 logarithm of Np, and (3) concatenating: (a) bits in least significant positions of a quantity resulting from the deleting in step (2), the quantity represented by LLx-LNp bits, and (b) bits in Y min in most significant positions, LLx being the base 2 logarithm of Lx.
12. The parallel processor as claimed in claim 7 , wherein the elementary processors are disposed according to the topology having one dimension, and the data structure is tridimensional, said data structure being defined as a function of X, Y and Z coordinates, and the position of the field of action for the at least one operand or for the at least one result is defined by X min, Y min, and Z min, and W min=X min+Lx*(Y min+Ly*Z min), where X min, Y min and Z min are minimum values of the X, Y, and Z coordinates, respectively, of elements of the field of action, Lx being the width of the tridimensional data structure along an X dimension, Ly being the width of the tridimensional data structure along a Y dimension, and W min is defined on said one dimension as a function of the X, Y, and Z coordinates of said position of the field of action.
13. The parallel processor as claimed in claim 12 , wherein when Np, Lx and Ly are powers of 2, an address Ad of an element of the data structure is calculated by steps: (1) adding X min and (Np−1−p), (2) deleting the last LNp bits of a result of the adding in step (1), LNp being the base 2 logarithm of Np, and (3) concatenating: (a) bits in least significant positions of a quantity resulting from the deleting in step (2), the quantity represented by LLx-LNp bits, (b) bits in medium significant positions of Y min represented by Ly bits, and (c) bits in most significant positions of Z min represented by Lz bits, LLx being the base 2 logarithm of Lx, and Lz being the width of the tridimensional data structure along a Z dimension.
14. The parallel processor as claimed in claim 7 , wherein the topology has one dimension, and the data structure has four dimensions, defined as a function of X, Y, Z and T coordinates, and the position of the field of action for the at least one operand or for the at least one result is defined by X min, Y min, Z min, and T min, such that W min=X min+Lx*(Y min+Ly*(Z min+Lz*T min)), where X min, Y min, Z min, and T min are minimum values of the X, Y, Z, and T coordinates of elements of the field of action, Lx being a width of the four dimensional data structure along an X dimension, Ly being a width of the four dimensional data structure along a Y dimension, Lz being a width of the four dimensional data structure along a Z dimension, and W min is defined on said one dimension as a function of the X, Y, Z, and T coordinates of said position of the field of action.
15. The parallel processor as claimed in claim 7 , wherein when the topology has at least three dimensions, and comprises a set {Nx, Ny, Nz, . . . } of the elementary processors, respectively, in each of the at least three dimensions, Nx, Ny, Nz being integers, the data structure is defined on at least three dimensions, Lx being the width of the at least three dimension data structure along an X dimension, Ly being the width of the at least three dimension data structure along a Y dimension, Lz being the width of the at least three dimension data structure along a Z dimension, and each element of the sets {Nx, Ny, Nz, . . . } and {Lx, Ly, Lz, . . . } are powers of 2, each element of a set {LLx, LLy, LLz, . . . } is the base 2 logarithm of corresponding elements of the set {Lx, Ly, Lz, . . . }, an address Ad of an element of the data structure being calculated by steps: (1) concatenating coordinates of the position of the field of action for the at least one operand or for the at least one result in a single word (w) with bits equal to a sum of elements of the set {LLx, LLy, LLz, . . . }, (2) swapping an order of the bits of the single word w to obtain a word w′, (3) splitting the word w′ into words of size equal to a size of the set {LLx, LLy, LLz, . . . }, the size being expressed in bits, such that a set indicated by {wx′, wy′, wz′, . . . } denotes the split words obtained, and for said each dimension of the topology: (a) adding (Nx−1−px) to wx′ of the set indicated by {wx′, wy′, wz′, . . . }, where px is a coordinate along the X dimension, of each of said elementary processors, (b) deleting the last LNx bits of a result of the adding in step (a) to obtain another result (Adx′), where LNx denotes the base 2 logarithm of Nx, (c) adding (Ny−1−py) to wy′ of the set indicated by {wx′, wy′, wz′, . . . }, where py is a coordinate along the Y dimension, of each of said elementary processors, (d) deleting last LNy bits from a result of the adding in step (c) to obtain another result (Ady′), where LNy denotes the base 2 logarithm of Ny, (f) adding (Nz−1−pz) to wz′ of the set indicated by {wx′, wy′, wz′, . . . }, where pz is a coordinate along the Z dimension, of each of said elementary processors, (g) deleting last LNz bits from a result of the adding in step (f) to obtain another result (Adz′), where LNz is the base 2 logarithm of Nz, and (h) swapping again an order of the bits of a set indicated by {Adx′, Ady′, Adz′, . . . } to obtain addresses Adx, Ady, and Adz in each of the at least three dimensions of the data structure, and (4) concatenating the addresses Adx, Ady, and Adz in a single word of the address Ad which represents the address relating to the field of action for the at least operand or for a result within each of the elementary processors.
17. The parallel processor as claimed in claim 16 , wherein Ly is a width of the bidimensional data structure along the Y dimension; and wherein when Nx, Ny, Lx and Ly are powers of 2, and LLx and LLy are the base 2 logarithms of Lx and Ly, respectively, an address Ad of an element of the data structure is calculated by steps: (1) adding X min and (Nx−1−px), (2) deleting the last LNx bits of a result of the adding in step (1), LNx being the base 2 logarithm of Nx, (3) adding Y min and (Ny−1−py), (4) deleting the last LNy bits of a result of the adding in step (3), LNy being the base 2 logarithm of Ny, and (5) concatenating: (a) bits in least significant positions of said Adx represented by LLx-LNx bits, and (b) bits in most significant positions of said Ady represented by LLy-LNy bits.
18. The parallel processor as claimed in claim 1 , wherein the parallel processor is of a Single Instruction Multiple Data (SIMD) type parallel processor.
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June 26, 2008
September 29, 2020
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