A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising: selecting a source chunk to be removed from a usable address space of a memory subsystem to distribute wear across all available chunks in the memory subsystem, the memory subsystem having a plurality of non-volatile memory components, the plurality of non-volatile memory components including a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem; copying valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem, the copying including a phase driven migration that tracks a pre-migration phase and a post-migration phase for the source chunk and the destination chunk; and updating a virtualization table to track assignment of the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.
2. The method of claim 1 , wherein selecting the source chunk includes identifying the source chunk using a rotation count and exchange pointer.
3. The method of claim 1 , further comprising: assigning the source chunk to the unusable address space of the memory subsystem.
4. The method of claim 1 , further comprising: determining whether policy criteria are met to trigger copying the valid data to the destination chunk.
5. The method of claim 1 , wherein copying valid data further comprising: performing the phase driven migration of the valid data to the destination chunk, the phase driven migration updating a pre-migration table with a phase bit per mapping and a post-migration table with a phase bit per mapping to track state of the migration.
6. The method of claim 1 , wherein selecting the chunk includes selecting a stripe of chunks to be migrated simultaneously.
7. The method of claim 1 , wherein updating the virtualization table to track assignment of the destination chunk includes updating the virtualization table to map a logical location of the destination chunks to a physical location for the destination chunk in the memory subsystem.
8. A memory subsystem implementing a process for wear-leveling, the memory subsystem comprising: a plurality of non-volatile memory components, the plurality of non-volatile memory components defining a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem; and a processor coupled to the plurality of non-volatile memory components, the processor to migrate valid data of a first chunk in a usable address space of the memory subsystem to a second chunk in the unusable address space of the memory subsystem to wear-level the plurality of non-volatile memory components, to update mapping information to enable indirect addressing of the data in the second chunk in the usable address space of the memory subsystem, and to update phase information to track each stage of a phase driven migration including a pre-migration phase and a post-migration phase for the first chunk and the second chunk.
9. The memory subsystem of claim 8 , wherein the processor is further to change a logical address mapping for the valid data from the first chunk to the second chunk.
10. The memory subsystem of claim 8 , wherein the processor is further to determine whether policy criteria are met to trigger migrating the valid data to the second chunk.
11. The memory subsystem of claim 8 , wherein the processor is further to implement migration of the valid data to the second chunk as the phase driven migration, the phase driven migration to update a pre-migration table with a phase bit per mapping and a post-migration table with a phase bit per mapping to track state of the migration.
12. The memory subsystem of claim 8 , wherein the processor is further to select a stripe of chunks including the first chunk to be migrated simultaneously.
13. The memory subsystem of claim 8 , wherein the processor is further to select a first chunk by using a rotation count and exchange pointer.
14. The memory subsystem of claim 8 , wherein the processor is further to update a virtualization table to map a logical location to a physical location for the data in the second chunk.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: move valid data of a source chunk in a usable address space of a memory subsystem to a destination chunk in unusable address space of the memory subsystem, distribute wear in the memory subsystem; track mapping data to enable physical address determination for the valid data in the destination chunk; and update phase information to track each stage of a phase driven migration including a pre-migration phase and a post-migration phase for the source chunk and the destination chunk.
16. The non-transitory computer-readable storage medium of claim 15 , the processing device further to: updating mapping data of the source chunk to indicate a location in the unusable address space of the memory subsystem.
17. The non-transitory computer-readable storage medium of claim 15 , the processing device further to: determine whether policy criteria are met to trigger moving the valid data to the destination chunk.
18. The non-transitory computer-readable storage medium of claim 15 , the processing device further to: update a pre-migration table with a phase bit per mapping data entry and a post-migration table with a phase bit per mapping data entry to track a state of the move of the valid data from the source chunk to the destination chunk.
19. The non-transitory computer-readable storage medium of claim 15 , moving the valid data of the source chunk is part of a simultaneous move of a stripe of source chunks to a strip of destination chunks in the memory subsystem.
20. The non-transitory computer-readable storage medium of claim 15 , the processing device further to: update the mapping data by updating a rotation count and exchange pointer.
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September 10, 2018
October 6, 2020
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