Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a die to operate in an overclocked mode; and circuitry to apply supplemental heat to the die while a die junction temperature is below an operating temperature range for the die junction temperature.
2. The apparatus of claim 1 , wherein the supplemental heat is applied if the die junction temperature is below the operating temperature range for the die junction temperature after liquid nitrogen or liquid helium is applied to the die.
3. The apparatus of claim 2 , wherein the supplemental heat is removed when the die junction temperature is within the operating temperature range for the die.
4. The apparatus of claim 1 , wherein the circuitry is included in the die and the die is a System on Chip.
5. The apparatus of claim 1 , wherein the circuitry includes a microcontroller communicatively coupled to the die.
6. The apparatus of claim 1 , wherein the die is a central processing unit die and the circuitry is in a chipset die.
7. The apparatus of claim 1 , wherein the circuitry is in a complex programmable logic device (CPLD).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 4, 2019
October 6, 2020
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