Described herein are mechanisms to inform a first Neighbor Awareness Networking (NAN) device as to whether or not a second NAN device is connected to a dynamic frequency selection (DFS) master and/or whether the second NAN device is listening to the same DFS master as the first NAN device. In order for NAN client devices to operate in the 5 GHz band and be DFS compliant, all such devices that are communicating in a NAN peer-to-peer manner must either maintain association with a DFS master or must listen to the same DFS master for channel information.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus for a Neighbor Awareness Network (NAN) device, the NAN device configurable for dynamic frequency selection (DFS), the apparatus comprising: memory and processing circuitry, wherein the processing circuitry is to: encode a NAN service discovery frame (SDF) to initiate a NAN operation, the NAN service discovery frame encoded to include a device capability attribute bit to indicate whether the NAN device is operating as a DFS master device; and if the NAN device is operating as the DFS master device, the processing circuitry is configured refrain from indicating available slots on a DFS channel unless permitted to use the DFS channel.
2. The apparatus of claim 1 wherein the processing circuitry is configured to: set the device capability attribute bit to one to indicate that the NAN device is operating as a DFS master device; and set the device capability attribute bit to zero otherwise.
3. The apparatus of claim 1 wherein if the NAN device is not operating as the DFS master, the processing circuitry is configured to decode a frame on a DFS channel from the DFS master, the frame to indicate available slots on the DFS channel as committed, potential, or conditional, the frame indicating the available slots when the DFS master is permitted to use the DFS channel.
4. The apparatus of claim 1 wherein if the NAN device is operating as the DFS master, the processing circuitry is configured to encode a frame for transmission on the DFS channel to a peer NAN device that indicates available slots on the DFS channel.
5. The apparatus of claim 4 , wherein the available slots are indicated as committed, potential, or conditional.
6. The apparatus of claim 1 , wherein if the NAN device is operating as the DFS master device, the processing circuitry is configured refrain from indicating available slots on a DFS channel unless permitted to use the DFS channel based on regulatory requirements.
7. The apparatus of claim 1 wherein the DFS channel in within an unlicensed 5 GHz band.
8. The apparatus of claim 1 , wherein the processing circuitry is to configure the NAN device for radar detection in an unlicensed band.
9. The apparatus of claim 1 further comprising a direct conversion mixer, the direct conversion mixer configured to directly downconvert RF signals to baseband signals, wherein the processing circuitry is configured to decode the baseband signals; and wherein the memory is to store the SDF frame.
10. The apparatus of claim 1 , further comprising a super-heterodyne mixer, the super-heterodyne mixer configured to downconvert RF signals to intermediate frequency signals prior to generation of baseband signals, wherein the processing circuitry is configured to decode the baseband signals; and wherein the memory is to store the SDF frame.
11. The apparatus of claim 1 further comprising: mixer circuitry to downconvert RF signal to baseband signals; and synthesizer circuitry, the synthesizer circuitry comprising one of a fractional-N synthesizer or a fractional N/N+1 synthesizer, the synthesizer circuitry configured to generate an output frequency for use by the mixer circuitry, wherein the processing circuitry is configured to decode the baseband signals.
12. The apparatus of claim 1 further comprising: mixer circuitry to downconvert RF signal to baseband signals; and synthesizer circuitry, the synthesizer circuitry comprising a delta-sigma synthesizer, the synthesizer circuitry configured to generate an output frequency for use by the mixer circuitry, wherein the processing circuitry is configured to decode the baseband signals.
13. A non-transitory computer-readable storage medium that stores instructions for execution by processing circuitry of a Neighbor Awareness Network (NAN) device to configure the NAN device to perform operations for dynamic frequency selection (DFS), the apparatus comprising: memory and processing circuitry, wherein the processing circuitry is to: encode a NAN service discovery frame (SDF) to initiate a NAN operation, the NAN service discovery frame encoded to include a device capability attribute bit to indicate whether the NAN device is operating as a DFS master device; and if the NAN device is operating as the DFS master device, the processing circuitry is configured refrain from indicating available slots on a DFS channel unless permitted to use the DFS channel.
14. The non-transitory computer-readable storage medium of claim 13 wherein the processing circuitry is configured to: set the device capability attribute bit to one to indicate that the NAN device is operating as a DFS master device; and set the device capability attribute bit to zero otherwise.
15. The non-transitory computer-readable storage medium of claim 13 wherein if the NAN device is not operating the DFS master, the processing circuitry is configured to decode a frame on a DFS channel from the DFS master, the frame to indicate available slots on the DFS channel as committed, potential, or conditional, when the DFS master is permitted to use the DFS channel.
16. The non-transitory computer-readable storage medium of claim 13 wherein if the NAN device is operating as the DFS master, the processing circuitry is configured to encode a frame for transmission on the DFS channel to a peer NAN device that indicates available slots on the DFS channel.
17. The apparatus of claim 16 , wherein the available slots are indicated as committed, potential, or conditional.
18. An apparatus for a Neighbor Awareness Network (NAN) device, the NAN device configurable for dynamic frequency selection (DFS), the apparatus comprising: memory and processing circuitry, wherein the processing circuitry is to: decode a NAN service discovery frame (SDF) received from another NAN device, the NAN service discovery frame indicating that the other NAN device is initiating a NAN operation, the NAN service discovery frame including a device capability attribute bit to indicate whether the other NAN device is operating as a DFS master device; and decode a frame received from the other NAN device, the frame to indicate available slots on a DFS channel if the other NAN device is permitted to use the DFS channel and not indicate available slots on the DFS channel if the other NAN devices is not permitted to use the DFS channel.
19. The apparatus of claim 18 wherein the device capability attribute bit is set to one to indicate that the other NAN device is operating as a DFS master device and is set to zero otherwise.
20. The apparatus of claim 18 wherein if the other NAN device is operating the DFS master, the processing circuitry is configured to decode a frame on a DFS channel from the other NAN device, the frame to indicate available slots on the DFS channel as committed, potential, or conditional, when the DFS master is permitted to use the DFS channel.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 30, 2019
October 6, 2020
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