A system includes a central processing unit (CPU) and components, a particular one of including logic to participate in a portion of a boot sequence of the system, where the portion of the boot sequence begins prior to activation of the CPU. The particular component is to send one or more signals to interact with another one of the components in the system during the portion of the boot sequence. The particular component includes a timer block to generate a set of timestamps during the portion of the boot sequence, where the set of timestamps indicates an amount of execution time of the particular component. The particular component sends the set of timestamps to the other component in a particular one of the one or more signals, where the set of timestamps are used to determine execution time of system components to complete the boot sequence.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a particular component to be included in a multi-component computing system, wherein the system is to comprise a host central processing unit (CPU) and the particular component comprises: logic comprising hardware circuitry to participate in a portion of a boot sequence of the system, wherein the portion of the boot sequence begins prior to activation of the host CPU, and the particular component is to send one or more signals to interact with an other component in the system during the portion of the boot sequence; a timer block to generate a set of timestamps during the portion of the boot sequence, wherein the set of timestamps indicates an amount of execution time of the particular component; and a transmitter to send the set of timestamps to the other component in a particular one of the one or more signals, wherein the set of timestamps are to be sent in association with determination of a total amount of execution time to complete the boot sequence.
2. The apparatus of claim 1 , wherein the logic is to cause the other component to be launched within the boot sequence.
3. The apparatus of claim 2 , wherein the particular signal follows a signal used to launch the other component.
4. The apparatus of claim 1 , wherein the particular component further comprises a microcontroller separate from the host CPU and is the first component to launch in the system to begin the boot sequence.
5. The apparatus of claim 4 , wherein the particular component comprises a power management controller (PMC).
6. The apparatus of claim 1 , wherein the set of timestamps comprises a second set of timestamps, the other component comprises a second component, and the particular component further comprises a receiver to receive one or more signals from a first component within the system during the portion of the boot sequence, wherein one of the signals received by the particular component from the first component comprises a first set of timestamps generated by the first component during the portion of the boot sequence.
7. The apparatus of claim 6 , wherein the timer block is further to adjust values in the second set of timestamps based on time values in the first set of timestamps, wherein values in the adjusted values in the second set of timestamps reflect an amount of time expired from an initiation of the boot sequence.
8. The apparatus of claim 6 , wherein the timer block is further to synchronize a clock of the particular component with a clock of the first component based on the first set of timestamps.
9. The apparatus of claim 6 , wherein the particular signal comprises both the first set of timestamps and the second set of timestamps.
10. The apparatus of claim 6 , wherein the particular component comprises a security engine and the logic are to implement functionality of the security engine.
11. The apparatus of claim 1 , wherein the other component comprises an interface to software running on the host CPU, the other component is to send the set of timestamps to the software, and the software is to determine a total execution time of the boot sequence.
12. The apparatus of claim 1 , wherein the particular component continues running in the boot sequence following the activation of the host CPU.
13. The apparatus of claim 1 , wherein the logic is implemented at least in part in firmware of the particular component.
14. At least one machine accessible storage medium having instructions stored thereon, the instructions when executed on a machine, cause the machine to: receive a first set of timing information from a first component in a multi-component computing system, wherein the first component comprises one of a set of components in the computing system to participate in a pre-boot portion of a boot sequence of the computing system, the pre-boot portion precedes activation of a host central processing unit (CPU) of the system, wherein the first set of timing information is received at a second component in the set of components; generate a second set of timing information at the second component, wherein the second set of timing information identifies a duration of the participation of the second component in the boot sequence; and send a signal from the second component to a third component in the computing system, wherein the signal comprises the first and second sets of timing information.
15. The storage medium of claim 14 , wherein the first and second sets of timing information each comprises a respective set of timestamps.
16. The storage medium of claim 14 , wherein the third component comprises an interface to software of the computing system, the third component participates in the boot sequence following activation of the host CPU, and the third component is to pass the first and second sets of timing information to the software.
17. The storage medium of claim 14 , wherein the instructions, when executed, further cause the machine to synchronize a clock of the second component based on the first timing information.
18. A system comprising: a central processing unit (CPU); a power management controller to participate in a pre-boot portion of boot flow of the system, wherein the pre-boot portion precedes and prepares for activation of the CPU; and a particular component to participate in the pre-boot portion of the boot flow of the system, wherein: the power management controller comprises: a first timer block to generate a first set of timestamps during the pre-boot portion of the boot sequence, wherein the first set of timestamps indicates a first duration of time measured from activation of the power management controller; and a transmitter to send a first signal to the particular component, wherein the first signal comprises timing information from the first set of timestamps; and the particular component comprises: a second timer block to generate a second set of timestamps during the pre-boot portion of the boot sequence, wherein the second set of timestamps indicates a second duration of time measured from activation of the particular component; and a transmitter to send a second signal to the CPU, wherein the second signal comprises timing information based on both the first set of timestamps and the second set of timestamps.
19. The system of claim 18 , wherein the particular component comprises a security engine to perform hardware-based security checks of the system.
20. The system of claim 18 , wherein the system comprises one of an in-vehicle computing system or an Internet of Things (IoT) device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 28, 2018
October 13, 2020
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