A quantum processing apparatus comprises control electronics, a switching unit, a bias line, and N electronic circuits. Both the switching unit and the bias line are connected to the control electronics. The N circuits comprise N respective, non-volatilely tunable resistors and N respective frequency-tunable, solid-state qubits. The control electronics are configured to individually tune the resistors via the switching unit, in a configuration mode of the apparatus; and apply a voltage bias to the electronic circuits via the bias line, in an operation mode of the apparatus. The electronic circuits are configured to passively apply respective bias signals to the qubits, wherein such bias signals are impacted by the resistors, in response to the voltage bias applied via the bias line, to operate the qubits at respective frequencies determined according to the respective bias signals.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A quantum processing apparatus, wherein the apparatus comprises: control electronics; a switching unit, connected to the control electronics; a bias line, connected to the control electronics; N electronic circuits, N>1, wherein the N circuits are connected, in parallel, to the control electronics via the bias line, and comprise: N respective, non-volatilely tunable resistors that are individually connected to the switching unit; and N respective frequency-tunable, solid-state qubits, each connected in series with a respective one of the N tunable resistors, wherein the control electronics are configured to: individually tune the resistors via the switching unit, in a configuration mode of the apparatus; and apply a voltage bias to the electronic circuits via the bias line, in an operation mode of the apparatus, and the electronic circuits are configured to passively apply respective bias signals to the qubits, in response to the voltage bias applied via the bias line, wherein such bias signals are impacted by the resistors as individually configured in the configuration mode, so as to operate the qubits at respective frequencies determined according to the respective bias signals.
2. The quantum processing apparatus according to claim 1 , wherein each of the non-volatilely tunable resistors comprises a gated memristive element that is connected to the switching unit via a gate.
3. The quantum processing apparatus according to claim 1 , wherein the electronic circuits comprise respective non-volatile transistors, the non-volatile transistors each comprising a respective one of the tunable resistors, wherein each of the non-volatile transistors has three terminals, which are connected to the switching unit, one of the qubits, and a ground, respectively.
4. The quantum processing apparatus according to claim 1 , wherein the tunable resistors comprise, each, an electrochemical, random access memory.
5. The quantum processing apparatus according to claim 1 , wherein the switching unit is a demultiplexer.
6. The quantum processing apparatus according to claim 1 , wherein the solid-state qubits are superconducting qubits configured as transmon-type qubits.
7. The quantum processing apparatus according to claim 1 , wherein each of the electronic circuits further comprises a non-tunable resistor, which is connected in series with a gate point of a respective one of the qubits and with a respective one of the tunable resistors, and the electronic circuits are configured to passively apply respective voltage biases to the qubits via the tunable resistors, in response to the voltage bias applied via the bias line, whereby each of the respective voltage biases applied is impacted by both the tunable resistor and the non-tunable resistor of each of the electronic circuits.
8. The quantum processing apparatus according to claim 1 , wherein in each of the electronic circuits, a respective one of the qubits is connected in series with a respective one of the tunable resistors, and the electronic circuits are configured to passively apply respective current signals to the qubits, in response to the voltage bias applied via the bias line, whereby each of the current signals applied is impacted by the tunable resistors of each of the electronic circuits.
9. The quantum processing apparatus according to claim 1 , wherein the apparatus comprises at least two platforms, the two platforms comprising a first platform adapted to be cooled down at a first temperature and a second platform adapted to be cooled down at a second temperature that is larger than the first temperature, and the qubits are arranged on the first platform, while the control electronics are arranged on the second platform.
10. The quantum processing apparatus according to claim 9 , wherein the apparatus comprises a third platform designed to be operated at room temperature, wherein the third platform comprises a computer connected to the control electronics.
11. The quantum processing apparatus according to claim 1 , wherein the control electronics comprise a field-programmable gate array.
12. The quantum processing apparatus according to claim 1 , wherein the quantum processing apparatus further comprises a signal generator unit and a switch matrix, the switch matrix connected to the signal generator unit, the signal generator unit connected to the control electronics.
13. The quantum processing apparatus according to claim 1 , wherein the qubits are each connected to a readout circuit connected to the control electronics.
14. The quantum processing apparatus according to claim 1 , wherein the N electronic circuits are monolithically integrated with the switching unit.
15. A method of operating a quantum processing apparatus, the method comprising providing a quantum processing apparatus with a switching unit, a bias line, and N electronic circuits, N>1, wherein the N circuits are connected, in parallel, to the control electronics via the bias line, and wherein the N circuits comprise: N respective, non-volatilely tunable resistors that are individually connected to the switching unit; and N respective frequency-tunable, solid-state qubits, each connected in series with a respective one of the N tunable resistors, individually tuning the resistors via the switching unit, in a configuration mode of the apparatus, and applying a voltage bias to the electronic circuits via the bias line, in an operation mode of the apparatus, to cause the electronic circuits to passively apply respective bias signals to the qubits, wherein such bias signals are impacted by the tunable resistors as individually configured in the configuration mode, so as to operate the qubits at respective frequencies determined according to the respective bias signals applied thereto.
16. The method according to claim 15 , wherein each of the electronic circuits of the apparatus further comprises a non-tunable resistor connected in series with a gate point of a respective one of the qubits and with a respective one of the tunable resistors, whereby applying the voltage bias to the electronic circuits via the bias line causes the electronic circuits to passively apply respective voltage biases to the qubits, wherein such voltage biases are impacted by the resistors.
17. The method according to claim 15 , wherein, in each of the electronic circuits of the apparatus, a respective one of the qubits is connected in series with a respective one of the tunable resistors, whereby applying the voltage bias to the electronic circuits via the bias line causes the electronic circuits to passively apply respective current signals to the qubits, the current signals being impacted by the tunable resistors.
18. The method according to claim 15 , wherein the apparatus comprises at least two platforms, the at least two platforms comprising a first platform in which the qubits are arranged and a second platform comprising the control electronics, the method further comprising cooling down the first platform at a first temperature and cooling down the second platform at a second temperature that is larger than the first temperature, in both the configuration mode and the operation mode of the apparatus.
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March 2, 2020
October 20, 2020
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