A semiconductor structure includes a die, a molding surrounding the die, a first seal ring disposed over the molding, and a second seal ring disposed below the molding. The semiconductor structure further includes a first interconnect structure disposed below the first surface of the die and a second interconnect structure disposed over the second surface and the molding. The first seal ring is disposed in the second interconnect structure and disposed over the molding, and the second seal ring is provided within the die and the first interconnect structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure, comprising: a die including a first surface and a second surface opposite to the first surface; a molding surrounding the die; a first seal ring disposed over the molding; and a second seal ring disposed below the molding.
2. The semiconductor structure of claim 1 , further comprising: a first dielectric layer disposed over the second surface of the die and over the molding; and a first conductive member disposed in the first dielectric layer, wherein the first seal ring is disposed in the first dielectric layer and surrounds the first conductive member.
3. The semiconductor structure of claim 1 , further comprising: a second dielectric layer disposed below the first surface of the die and over the molding; and a second conductive member disposed in the second dielectric layer, wherein the second seal ring is disposed in the second dielectric layer and surrounds the second conductive member.
4. The semiconductor structure of claim 1 , wherein a width of the first seal ring is substantially greater than a width of the second seal ring.
5. The semiconductor structure of claim 1 , further comprising: a third dielectric layer disposed below the first surface of the die and surrounded by the molding; and a third conductive member disposed in the third dielectric layer, wherein the third dielectric layer and the third conductive member are disposed between the die and the second dielectric layer, and the third conductive member is electrically connected to the second conductive member.
6. A semiconductor structure, comprising: a die including a first surface and a second surface opposite to the first surface; a first interconnect structure disposed below the first surface of the die; a molding surrounding the die and the first interconnect structure; a second interconnect structure disposed over the second surface and the molding; a first seal ring disposed in the second interconnect structure and disposed over the molding; and a second seal ring provided within the die and the first interconnect structure.
7. The semiconductor structure of claim 6 , wherein the first interconnect structure further comprises a first dielectric layer disposed below the first surface of the die and a first conductive member disposed within the first dielectric layer.
8. The semiconductor structure of claim 7 , wherein the second seal ring comprises a first portion and a second portion, the first portion of the second seal ring vertically extended within the die, and the second portion of the second seal ring vertically extended within the first dielectric layer of the first interconnect structure.
9. The semiconductor structure of claim 8 , wherein the first portion of the second seal ring is disposed adjacent to the edge of the die or the molding, and the second portion of the second seal ring is disposed adjacent to the edge of the first dielectric layer or the molding.
10. The semiconductor structure of claim 6 , wherein the second interconnect structure further comprises a second dielectric layer disposed over the second surface of the die and a second conductive member disposed within the second dielectric layer, and the first seal ring is disposed within the second dielectric layer.
11. The semiconductor structure of claim 10 , wherein the first seal ring is separated from the second conductive member by the second dielectric layer.
12. The semiconductor structure of claim 10 , wherein the first seal ring is in contact with the second conductive member of the second interconnect structure.
13. The semiconductor structure of claim 6 , wherein a width of the first seal ring is substantially greater than a width of the second seal ring.
14. A semiconductor structure comprising: a die including a first surface and a second surface opposite to the first surface; a first interconnect structure disposed below the first surface of the die; a molding surrounding the die and the first interconnect structure; a second interconnect structure disposed over the second surface of the die and the molding; a third interconnect structure disposed below the first interconnect structure and molding; a first seal ring disposed in the second interconnect structure and disposed over the molding; a second seal ring vertically extended within the die and the first interconnect structure; and a third seal ring disposed in the third interconnect structure and disposed over the molding.
15. The semiconductor structure of claim 14 , the first interconnect structure further comprises a first dielectric layer disposed below the first surface of the die and a first conductive member disposed within the first dielectric layer.
16. The semiconductor structure of claim 15 , wherein a portion of the second seal ring vertically extended within the die, and another portion of the second seal ring vertically extended within the first dielectric layer of the first interconnect structure.
17. The semiconductor structure of claim 14 , wherein the second interconnect structure further comprises a second dielectric layer disposed over the second surface of the die and a second conductive member disposed within the second dielectric layer, and the first seal ring is disposed within the second dielectric layer.
18. The semiconductor structure of claim 14 , wherein the third interconnect structure further comprises a third dielectric layer disposed below the first surface of the die and a third conductive member disposed within the third dielectric layer, and the third seal ring is disposed within the third dielectric layer.
19. The semiconductor structure of claim 14 , wherein a width of the first seal ring is substantially greater than a width of the second seal ring.
20. The semiconductor structure of claim 14 , wherein a width of the first seal ring is substantially greater than a width of the third seal ring.
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June 14, 2019
October 27, 2020
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