Shift register circuit, gate driving circuit and method for driving the same, and display apparatus

1. A shift register circuit, comprising: an input circuit electrically coupled to a pull-up node of the shift register circuit, and configured to receive an input signal and output the input signal to the pull-up node; an output circuit electrically coupled to a signal output terminal and the pull-up node of the shift register circuit, and configured to receive a clock signal and provide an output signal at the signal output terminal based on the clock signal under control of a level at the pull-up node; a pull-down circuit electrically coupled to the signal output terminal and a pull-down node of the shift register circuit, and configured to pull down a level at the signal output terminal under control of a level at the pull-down node; and at least one of: a feedback circuit electrically coupled to the pull-up node, and configured to output a first feedback signal based on the level at the pull-up node; or a pull-down control circuit electrically coupled to the pull-up node and the pull-down node, and configured to receive a second feedback signal and control the level at the pull-down node under control of the level at the pull-up node and the second feedback signal.

2. The shift register circuit according to claim 1 , wherein the pull-down control circuit is included and comprises: a first control sub-circuit electrically coupled to the pull-up node and the pull-down node, and configured to control the level at the pull-down node under control of the level at the pull-up node; and a second control sub-circuit electrically coupled to the first control sub-circuit, wherein the second control sub-circuit has a feedback input terminal, and is configured to receive the second feedback signal at the feedback input terminal and control turn-on and turn-off of the first control sub-circuit according to the second feedback signal.

3. The shift register circuit according to claim 1 , wherein the shift register circuit comprises one of the feedback circuit or the pull-down control circuit, and the pull-down node comprises a first pull-down node.

4. The shift register circuit according to claim 1 , wherein: the shift register circuit comprises the feedback circuit and the pull-down control circuit; the pull-down node comprises a first pull-down node and a second pull-down node; the pull-down circuit is electrically coupled to the signal output terminal, the first pull-down node and the second pull-down node, and is configured to pull down the level at the signal output terminal under control of levels at the first pull-down node and the second pull-down node; and the pull-down control circuit is electrically coupled to the pull-up node and the first pull-down node, and is configured to receive the second feedback signal and control the level at the first pull-down node under control of the level at the pull-up node and the second feedback signal.

5. The shift register circuit according to claim 4 , wherein the pull-down control circuit comprises a first control sub-circuit and a second control sub-circuit, and wherein: the first control sub-circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a capacitor, wherein: the first transistor has a gate electrically coupled to a power supply signal terminal configured to provide a power supply signal, a first electrode electrically coupled to the gate, and a second electrode electrically coupled to a gate of the second transistor; the second transistor has the gate electrically coupled to the second electrode of the first transistor, a first electrode electrically coupled to the power supply signal terminal, and a second electrode electrically coupled to the first pull-down node; the third transistor has a gate electrically coupled to the pull-up node, a first electrode electrically coupled to the second electrode of the second transistor, and a second electrode electrically coupled to a reference signal terminal configured to provide a reference signal; the fourth transistor has a gate electrically coupled to the pull-up node, a first electrode electrically coupled to the second electrode of the first transistor, and a second electrode electrically coupled to the reference signal terminal; and the capacitor is electrically coupled between the gate and the second electrode of the second transistor, and the second control sub-circuit comprises a fifth transistor, wherein the fifth transistor has a gate electrically coupled to the feedback input terminal, a first electrode electrically coupled to the second electrode of the first transistor, and a second electrode electrically coupled to the reference signal terminal.

6. The shift register circuit according to claim 4 , wherein the feedback circuit comprises a feedback sub-circuit, a first pull-down sub-circuit, and a second pull-down sub-circuit, and wherein: the feedback sub-circuit comprises a sixth transistor and a seventh transistor, wherein the sixth transistor has a gate electrically coupled to the pull-up node, a first electrode electrically coupled to a power supply signal terminal configured to provide a power supply signal, and a second electrode electrically coupled to a gate of the seventh transistor, and the seventh transistor has the gate electrically coupled to a first electrode thereof, and a second electrode electrically coupled to a feedback output terminal; the first pull-down sub-circuit comprises an eighth transistor and an eleventh transistor, wherein the eighth transistor has a gate electrically coupled to the first pull-down node, a first electrode electrically coupled to the second electrode of the sixth transistor, and a second electrode electrically coupled to a reference signal terminal configured to provide a reference signal, and the eleventh transistor has a gate electrically coupled to the second pull-down node, a first electrode electrically coupled to the second electrode of the sixth transistor, and a second electrode electrically coupled to the reference signal terminal; and the second pull-down sub-circuit comprises a ninth transistor and a twelfth transistor, wherein the ninth transistor has a gate electrically coupled to the first pull-down node, a first electrode electrically coupled to the pull-up node, and a second electrode electrically coupled to the reference signal terminal, and the twelfth transistor has a gate electrically coupled to the second pull-down node, a first electrode electrically coupled to the pull-up node, and a second electrode electrically coupled to the reference signal terminal.

7. The shift register circuit according to claim 6 , wherein the feedback circuit further comprises a third pull-down sub-circuit, the third pull-down sub-circuit comprising a tenth transistor and a thirteenth transistor, wherein: the tenth transistor has a gate electrically coupled to the first pull-down node, a first electrode electrically coupled to the second electrode of the ninth transistor and the feedback output terminal, and a second electrode electrically coupled to the reference signal terminal; and the thirteenth transistor has a gate electrically coupled to the second pull-down node, a first electrode electrically coupled to the second electrode of the twelfth transistor and the feedback output terminal, and a second electrode electrically coupled to the reference signal terminal.

8. The shift register circuit according to claim 1 , wherein the feedback circuit is included and comprises: a feedback sub-circuit electrically coupled to the pull-up node, wherein the feedback sub-circuit has a feedback output terminal, and is configured to generate the first feedback signal based on the level at the pull-up node and output the first feedback signal at the feedback output terminal; a first pull-down sub-circuit electrically coupled to the feedback sub-circuit and the pull-down node, and configured to pull down the first feedback signal generated by the feedback sub-circuit under control of the level at the pull-down node; and a second pull-down sub-circuit electrically coupled to the pull-up node and the pull-down node, and configured to pull down the level at the pull-up node under control of the level at the pull-down node.

9. The shift register circuit according to claim 8 , wherein the feedback circuit further comprises a third pull-down sub-circuit, wherein the second pull-down sub-circuit is electrically coupled to a reference signal terminal configured to provide a reference signal through the third pull-down sub-circuit, and the third pull-down sub-circuit is electrically coupled to the pull-down node, and is configured to pull down a level at a node between the third pull-down sub-circuit and the second pull-down sub-circuit under control of the level at the pull-down node; and the feedback output terminal is electrically coupled to the node between the third pull-down sub-circuit and the second pull-down sub-circuit.

10. The shift register circuit according to claim 9 , wherein the input circuit comprises a fourteenth transistor and a fifteenth transistor, wherein the fourteenth transistor has a gate and a first electrode electrically coupled to a signal input terminal configured to provide an input signal, and a second electrode electrically coupled to a first electrode of the fifteenth transistor, and the fifteenth transistor has a gate electrically coupled to the gate of the fourteenth transistor, the first electrode electrically coupled to the second electrode of the fourteenth transistor, and a second electrode electrically coupled to the pull-up node; and the feedback output terminal is electrically coupled to the second electrode of the fourteenth transistor and the first electrode of the fifteenth transistor.

11. The shift register circuit according to claim 9 , further comprising a reset circuit comprising a sixteenth transistor and a seventeenth transistor, wherein: the sixteenth transistor has a gate electrically coupled to a reset signal terminal configured to provide a reset signal, a first electrode electrically coupled to the pull-up node, and a second electrode electrically coupled to a first electrode of the seventeenth transistor; the seventeenth transistor has a gate electrically coupled to the reset signal terminal, the first electrode electrically coupled to the second electrode of the sixteenth transistor, and a second electrode electrically coupled to the reference signal terminal; and the feedback output terminal is electrically coupled to the second electrode of the sixteenth transistor and the first electrode of the seventeenth transistor.

12. A gate driving circuit, comprising cascaded shift register circuits at N stages according to claim 1 , wherein: the shift register circuit at the n th stage receives an output signal from the shift register circuit at the (n−1) th stage as an input signal, and receives an output signal from the shift register circuit at the (n+2) th stage as a reset signal, where n and N are integers, N≥4, and 2≤n<N−2; for each shift register circuit having a pull-down control circuit, the shift register circuit at its next stage has a feedback circuit, and the shift register circuit having the pull-down control circuit receives a first feedback signal output from the feedback circuit of the shift register circuit at its next stage as a second feedback signal; and a pull-down node of the shift register circuit having the pull-down control circuit is electrically coupled to a pull-down node of the shift register circuit at its previous or next stage to form a group of shift register circuits.

13. The gate driving circuit according to claim 12 , wherein: the pull-down node comprises a first node; and one shift register circuit from the group of shift register circuits comprises a pull-down control circuit, and another shift register circuit from the group of shift register circuits comprises a feedback circuit.

14. The gate driving circuit according to claim 12 , wherein: the pull-down node comprises a first node and a second node; each shift register circuit from the group of shift register circuits comprises a pull-down control circuit and a feedback circuit; and a first pull-down node of a first shift register circuit from the group of shift register circuits is electrically coupled to a second pull-down node of a second shift register circuit from the group of shift register circuits, and a second pull-down node of the first shift register circuit from the group of shift register circuits is electrically coupled to a first pull-down node of the second shift register circuit from the group of shift register circuits.

15. The gate driving circuit according to claim 14 , wherein a pull-down control circuit of the first shift register circuit from the group of shift register circuits is configured to be powered by a first power supply signal, and a pull-down control circuit of the second shift register circuit from the group of shift register circuits is configured to be powered by a second power supply signal which is inverted to the first power supply signal.

16. The gate driving circuit according to claim 12 , wherein the shift register circuit having the feedback circuit has a feedback output terminal configured to output the first feedback signal, and the gate driving circuit further comprises a connection component provided between the feedback output terminal and the pull-up node of the shift register circuit, and configured to electrically couple the feedback output terminal to the pull-up node in a first state, and electrically decouple the feedback output terminal from the pull-up node in a second state.

17. The gate driving circuit according to claim 16 , wherein the connection component comprises a pad which is able to be electrically coupled by laser breakdown.

18. A display apparatus, comprising the gate driving circuit according to claim 12 .

19. A method for driving the gate driving circuit according to claim 12 , comprising: providing power to pull-down control circuits and/or feedback circuits of the shift register circuits in the gate driving circuit, and providing clock signals to the shift register circuits.

20. The method according to claim 19 , wherein the pull-down node comprises a first node and a second node and each shift register circuit in the group of shift register circuits comprises a pull-down control circuit and a feedback circuit, and wherein providing power to the pull-down control circuits of the shift register circuits comprises: providing a first power supply signal to a pull-down control circuit of a first shift register circuit from the group of shift register circuits, and providing a second power supply signal to a pull-down control circuit of a second shift register circuit from the group of shift register circuits, wherein: in a first time period, the first power supply signal is at a first level, and the second power supply signal is at a second level; and in a second time period, the first power supply signal is at the second level, and the second power supply signal is at the first level.