Equalizer circuit

1. An equalizer circuit, comprising: a first arithmetic circuit, configured to compensate an equalization sequence by a plurality of secondary feedback sequences to output a first added sequence; a second arithmetic circuit, configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence; a data sampling circuit, comprising: a primary sequence circuit, configured to sample the second added sequence according to a data clock to output a primary sequence, the primary sequence circuit gaining the primary sequence to output the primary feedback sequence; and a plurality of secondary sequence circuits, configured to sequentially sample the primary sequence according to the data clock to output a plurality of secondary sequences, the secondary sequence circuits gaining the corresponding secondary sequences to output the secondary feedback sequences; and an edge sampling circuit, configured to sample the first added sequence according to an edge clock to output an edge sequence.

2. The equalizer circuit according to claim 1 , wherein a rate of the equalization sequence is substantially twice a rate of the data clock, and the rate of the equalization sequence is substantially twice a rate of the edge clock, the primary feedback sequence comprises a first primary feedback sub-sequence and a second primary feedback sub-sequence, and the second added sequence comprises a first added sub-sequence and a second added sub-sequence; the second arithmetic circuit comprises a first arithmetic sub-circuit and a second arithmetic sub-circuit, the first arithmetic sub-circuit being configured to compensate the first added sequence the first primary feedback sub-sequence to output the first added sub-sequence, and the second arithmetic sub-circuit being configured to compensate the first added sequence the second primary feedback sub-sequence to output the second added sub-sequence; the primary sequence circuit comprises: a first primary sequence sub-circuit, configured to sample the first added sub-sequence according to the data clock to output a first primary sub-sequence, the first primary sub-sequence circuit gaining the first primary sub-sequence to output the first primary feedback sub-sequence; and a second primary sequence sub-circuit, configured to sample the second added sub-sequence according to an inverse of the data clock to output a second primary sub-sequence, the second primary sequence sub-circuit gaining the second primary sub-sequence to output the second primary feedback sub-sequence; the data sampling circuit comprises four of the plurality of secondary sequence circuits, the four secondary sequence circuits are a first secondary sequence sub-circuit, a second secondary sequence sub-circuit, a third secondary sequence sub-circuit, and a fourth secondary sequence sub-circuit; the first secondary sequence sub-circuit being configured to sample the first primary sub-sequence according to the inverse of the data clock to output a first secondary sub-sequence, and the first secondary sequence sub-circuit gaining the first secondary sub-sequence to output a first secondary feedback sub-sequence; the second secondary sequence sub-circuit being configured to sample the second primary sub-sequence according to the data clock to output a second secondary sub-sequence, and the second secondary sequence sub-circuit gaining the second secondary sub-sequence to output a second secondary feedback sub-sequence; the third secondary sequence sub-circuit being configured to sample the first secondary sub-sequence according to the inverse of the data clock to output a third secondary sub-sequence, and the third secondary sequence sub-circuit gaining the third secondary sub-sequence to output a third secondary feedback sub-sequence; the fourth secondary sequence sub-circuit being configured to sample the second secondary sub-sequence according to the data clock to output a fourth secondary sub-sequence, and the fourth secondary sequence sub-circuit gaining the fourth secondary sub-sequence to output a fourth secondary feedback sub-sequence; and the first arithmetic circuit is configured to compensate the equalization sequence by the first secondary feedback sub-sequence, the second secondary feedback sub-sequence, the third secondary feedback sub-sequence, and the fourth secondary feedback sub-sequence, to output the first added sequence.

3. The equalizer circuit according to claim 2 , wherein the edge sampling circuit comprises a plurality of edge trigger sampling circuits, the plurality of edge trigger sampling circuits sequentially sample the first added sequence according to the edge clock to output the edge sequence, and a number of the edge trigger sampling circuits is equal to a number of the sequence circuits.

4. The equalizer circuit according to claim 2 , wherein the first primary sequence sub-circuit comprises: a first primary trigger sampling sub-circuit, configured to sample the first added sub-sequence according to the data clock to output the first primary sub-sequence; and a first primary gain sub-circuit, configured to gain the first primary sub-sequence by a first primary sub-magnification to output the first primary feedback sub-sequence; the second primary sequence sub-circuit comprises: a second primary trigger sampling sub-circuit, configured to sample the second added sub-sequence according to the inverse of the data clock to output the second primary sub-sequence; and a second primary gain sub-circuit, configured to gain the second primary sub-sequence by a second primary sub-magnification to output the second primary feedback sub-sequence; and the first primary sub-magnification and the second primary sub-magnification each is a constant between −1 and 0.

5. The equalizer circuit according to claim 4 , wherein the edge sampling circuit comprises a plurality of edge trigger sampling circuits, the plurality of edge trigger sampling circuits sequentially sample the first added sequence according to the edge clock to output the edge sequence, and a number of the plurality of edge trigger sampling circuits being equal to a number of the sequence circuits.

6. The equalizer circuit according to claim 4 , wherein each of the trigger sampling circuits is a D-type flip flop, a phase of the data clock substantially differing from a phase of the edge clock by about 90 degrees, and each of the arithmetic circuits being an adder.

7. The equalizer circuit according to claim 4 , wherein the first secondary sequence sub-circuit comprises: a first secondary trigger sampling sub-circuit, configured to sample the first primary sub-sequence according to the inverse of the data clock to output the first secondary sub-sequence; and a first secondary gain sub-circuit, configured to gain the first secondary sub-sequence by a first secondary sub-magnification to output the first secondary feedback sub-sequence; the second secondary sequence sub-circuit comprises: a second secondary trigger sampling sub-circuit, configured to sample the second primary sub-sequence according to the data clock to output the second secondary sub-sequence; and a second secondary gain sub-circuit, configured to gain the second secondary sub-sequence by a second secondary sub-magnification to output the second secondary feedback sub-sequence; the third secondary sequence sub-circuit comprises: a third secondary trigger sampling sub-circuit, configured to sample the first secondary sub-sequence according to the inverse of the data clock to output the third secondary sub-sequence; and a third secondary gain sub-circuit, configured to gain the third secondary sub-sequence at a third secondary sub-magnification to output the third secondary feedback sub-sequence; the fourth secondary sequence sub-circuit comprises: a fourth secondary trigger sampling sub-circuit, configured to sample the second primary sub-sequence according to the data clock to output the fourth secondary sub-sequence; and a fourth secondary gain sub-circuit, configured to gain the fourth secondary sub-sequence by a fourth secondary sub-magnification to output the fourth secondary feedback sub-sequence; and the first secondary sub-magnification, the second secondary sub-magnification, the third secondary sub-magnification, and the fourth secondary sub-magnification each being a constant between −1 and 0.

8. The equalizer circuit according to claim 7 , wherein the edge sampling circuit comprises a plurality of edge trigger sampling circuits, the plurality of edge trigger sampling circuits sequentially sample the first added sequence according to the edge clock to output the edge sequence, and a number of the edge trigger sampling circuits is equal to a number of the sequence circuits.

9. The equalizer circuit according to claim 7 , wherein each of the trigger sampling circuits is a D-type flip flop, a phase of the data clock substantially differs from a phase of the edge clock by about 90 degrees, and each of the arithmetic circuits is an adder.

10. The equalizer circuit according to claim 7 , wherein a magnification value of the first secondary sub-magnification at a high level of the inverse of the data clock is different from a magnification value of the first secondary sub-magnification at a low level of the inverse of the data clock; a magnification value of the second secondary sub-magnification at a high level of the data clock is different from a magnification value of the second secondary sub-magnification at a low level of the data clock; a magnification value of the third secondary sub-magnification at the high level of the inverse of the data clock is different from a magnification value of the third secondary sub-magnification at the low level of the inverse of the data clock; and a magnification value of the fourth secondary sub-magnification at the high level of the data clock is different from a magnification value of the fourth secondary sub-magnification at the low level of the data clock.

11. The equalizer circuit according to claim 10 , wherein each of the trigger sampling circuits is a D-type flip flop, a phase of the data clock substantially differing from a phase of the edge clock by about 90 degrees, and each of the arithmetic circuits being an adder.