Techniques for parallel power down processing of an integrated circuit (IC) design are described herein. An aspect includes receiving IC design information comprising a plurality of IC elements. Another aspect includes identifying a plurality of timing endpoints in the IC design information. Another aspect includes determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints. Another aspect includes performing power down processing of net drivers in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer-implemented method comprising: receiving, by a processor, integrated circuit (IC) design information comprising a plurality of IC elements; identifying a plurality of timing endpoints in the IC design information; determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints; and performing power down processing of the plurality of IC elements in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel, and wherein performing the power down processing of the plurality of IC elements in the plurality of nets comprises: determining a number of available threads; assigning the plurality of nets among the available threads, wherein the assigning is performed such that a number of gates assigned to each thread of the available threads is balanced; and performing, by each of the available threads, power down processing of the plurality of nets assigned to each thread of the available threads.
2. The method of claim 1 , wherein identifying the plurality of timing endpoints in the IC design information comprises: identifying a sink in the IC design information; tracing from the sink back to a source of the IC design information.
3. The method of claim 1 , wherein a timing endpoint of the plurality of timing endpoints comprises a latch.
4. The method of claim 1 , wherein determining a net of the plurality of nets comprises: determining a set of IC elements located directly between two timing endpoints of the plurality of timing endpoints, wherein the set of IC elements comprises the net.
5. The method of claim 1 , further comprising: ordering the plurality of nets from a sink to a source of the IC design information before performing the power down processing in order to assign a level to each of the plurality of nets, wherein the power down processing of the plurality of nets assigned to a same level is performed in parallel.
6. The method of claim 1 , wherein the power down processing comprises at least one of reducing a size of a buffer in the IC design information, reducing a threshold voltage of a transistor in the IC design information, selecting of a smaller level for a multiple power level gate, and reducing a size of a transistor of the IC design information; and wherein the power down processing is performed based on an amount of slack in a net that is being processed.
7. A system comprising: a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising: receiving integrated circuit (IC) design information comprising a plurality of IC elements; identifying a plurality of timing endpoints in the IC design information; determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints; and performing power down processing of the plurality of IC elements in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel, and wherein performing the power down processing of the plurality of IC elements in the plurality of nets comprises: determining a number of available threads; assigning the plurality of nets among the available threads, wherein the assigning is performed such that a number of gates assigned to each thread of the available threads is balanced; and performing, by each of the available threads, power down processing of the plurality of nets assigned to each thread of the available threads.
8. The system of claim 7 , wherein identifying the plurality of timing endpoints in the IC design information comprises: identifying a sink in the IC design information; tracing from the sink back to a source of the IC design information.
9. The system of claim 7 , wherein a timing endpoint of the plurality of timing endpoints comprises a latch.
10. The system of claim 7 , wherein determining a net of the plurality of nets comprises: determining a set of IC elements located directly between two timing endpoints of the plurality of timing endpoints, wherein the set of IC elements comprises the net.
11. The system of claim 7 , the operations further comprising: ordering the plurality of nets from a sink to a source of the IC design information before performing the power down processing in order to assign a level to each of the plurality of nets, wherein the power down processing of the plurality of nets assigned to a same level is performed in parallel.
12. The system of claim 7 , wherein the power down processing comprises at least one of reducing a size of a buffer in the IC design information, reducing a threshold voltage of a transistor in the IC design information, selecting of a smaller level for a multiple power level gate, and reducing a size of a transistor of the IC design information; and wherein the power down processing is performed based on an amount of slack in a net that is being processed.
13. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising: receiving integrated circuit (IC) design information comprising a plurality of IC elements; identifying a plurality of timing endpoints in the IC design information; determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints; and performing power down processing of the plurality of IC elements in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel, and wherein performing the power down processing of the plurality of IC elements in the plurality of nets comprises: determining a number of available threads; assigning the plurality of nets among the available threads, wherein the assigning is performed such that a number of gates assigned to each thread of the available threads is balanced; and performing, by each of the available threads, power down processing of the plurality of nets assigned to each thread of the available threads.
14. The computer program product of claim 13 , wherein identifying the plurality of timing endpoints in the IC design information comprises: identifying a sink in the IC design information; tracing from the sink back to a source of the IC design information.
15. The computer program product of claim 13 , wherein a timing endpoint of the plurality of timing endpoints comprises a latch.
16. The computer program product of claim 13 , wherein determining a net of the plurality of nets comprises: determining a set of IC elements located directly between two timing endpoints of the plurality of timing endpoints, wherein the set of IC elements comprises the net.
17. The computer program product of claim 13 , the operations further comprising: ordering the plurality of nets from a sink to a source of the IC design information before performing the power down processing in order to assign a level to each of the plurality of nets, wherein the power down processing of the plurality of nets assigned to a same level is performed in parallel.
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August 14, 2019
November 10, 2020
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