Techniques to improve critical dimension width and depth uniformity between features with different layout densities

1. A method of forming a contact structure, the method comprising the steps of: patterning features in at least two different regions of a dielectric at different layout densities whereby, due to etch loading effects, the features are patterned to different depths in the dielectric and have different bottom dimensions; depositing a sacrificial spacer into and lining the features whereby, due to the features having the different bottom dimensions, some of the features are pinched-off by the sacrificial spacer; opening up the sacrificial spacer at bottoms of one or more the features that are not pinched-off by the sacrificial spacer; selectively extending the one or more features in the dielectric, such that the one or more features have a discontinuous taper with a stepped sidewall profile; removing the sacrificial spacer; and filling the features with a conductive material to form the contact structure.

2. The method of claim 1 , wherein the features are selected from the group consisting of: vias, trenches, and combinations thereof.

3. The method of claim 1 , wherein the sacrificial spacer comprises a material selected from the group consisting of: silicon nitride (SiN), titanium oxide (TiOx), amorphous silicon (aSi), and combinations thereof.

4. The method of claim 1 , wherein the sacrificial spacer is deposited to a thickness of from about 2 nm to about 10 nm and ranges therebetween.

5. The method of claim 1 , wherein the dielectric is present over a metal layer (Mx).

6. The method of claim 5 , wherein a capping layer separates the metal layer from the dielectric.

7. The method of claim 1 , further comprising the steps of: patterning a feature A in an isolated region of the dielectric, features B in a semi-isolated region of the dielectric, and features C in a dense region of the dielectric, wherein a layout density of feature A is less than a layout density of features B, and wherein a layout density of features B is less than a layout density of features C.

8. The method of claim 7 , wherein the feature A is patterned to a depth D A in the dielectric, the features B are patterned to a depth D B in the dielectric, and the features C are patterned to a depth D C in the dielectric, and wherein D A <D B <D C .

9. The method of claim 7 , wherein the feature A has a bottom critical dimension (CD) CD A, the features B have a bottom critical dimension CD B, and the features C have a bottom critical dimension CD C, and wherein CD A>CD B>CD C.

10. The method of claim 7 , wherein the sacrificial spacer has a thickness T A at a bottom of the feature A, the sacrificial spacer has a thickness T B at bottoms of the features B, and the sacrificial spacer has a thickness T C at bottoms of the features C, and wherein T C >T B >T A .

11. The method of claim 7 , wherein the features A and B are not pinched-off by the sacrificial spacer, and wherein the features C are pinched off by the sacrificial spacer.

12. The method of claim 7 , wherein the features A and B are selectively extended in the dielectric.

13. The method of claim 7 , wherein the features A and B have the discontinuous taper with the stepped sidewall profile.

14. The method of claim 7 , wherein the features C have a continuous taper.

15. The method of claim 1 , wherein the conductive material comprises a contact metal selected from the group consisting of: nickel (Ni), platinum (Pt), copper (Cu), gold (Au), and combinations thereof.