A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A clock alignment system comprising: a clock generator configured to generate a first clock signal in a first clock domain to drive a first data circuit in the first clock domain; a second data circuit in a second clock domain slower than the first clock domain, the second data circuit being configured to generate a second clock signal and to transfer data to or from the first data circuit in synchronization with the second clock signal; a coarse delay-locked loop (DLL) configured to generate third clock signals having corresponding phase offsets from the first clock signal, and to output a selected one of the third clock signals, wherein the coarse DLL has glitch-less switching between outputting consecutive ones of the third clock signals; a fine DLL configured to generate a fourth clock signal to drive the second data circuit, by adjusting a phase of the selected third clock signal; and a control circuit configured to align the phases of the first and second clock signals by selecting the one of the third clock signals and controlling the phase adjustment of the selected third clock signal.
2. The system of claim 1 , wherein the coarse DLL comprises a plurality of pass transistors to blend the consecutive ones of the third clock signals during the glitch-less switching.
3. The system of claim 1 , wherein the control circuit has an unlimited phase acquisition range of the first and second clock signals.
4. The system of claim 1 , wherein there are more than four third clock signals generated by the coarse DLL, the third clock signals are evenly spaced and span the clock period of the first clock signal, and the fine DLL has a phase adjustment range of at least twice and no more than four times the spacing of the third clock signals.
5. The system of claim 1 , wherein the number of third clock signals exceeds the ratio of the speed of the first clock domain to the speed of the second clock domain.
6. The system of claim 1 , further comprising a phase detector in the first clock domain, to compare the phases of the first and second clock signals, wherein the control circuit aligns the phases of the first and second clock signals by using the compared phases.
7. The system of claim 6 , further comprising: a first clock divider in the first clock domain and configured to divide the first clock signal; and a second clock divider in the second data circuit and configured to generate the second clock signal by dividing the fourth clock signal, wherein the phase detector is configured to compare the phases of the first and second clock signals by comparing the phase of the divided first clock signal to the phase of the second clock signal.
8. A method of clock alignment, the method comprising: generating, by a clock generator in a first clock domain, a first clock signal to drive a first data circuit in the first clock domain; generating a second clock signal by a second data circuit in a second clock domain slower than the first clock domain; transferring, by the second data circuit, data to or from the first data circuit in synchronization with the second clock signal; generating, by a coarse delay-locked loop (DLL), third clock signals having corresponding phase offsets from the first clock signal; outputting, by the coarse DLL, a selected one of the third clock signals; generating, by a fine DLL, a fourth clock signal to drive the second data circuit, by adjusting a phase of the selected third clock signal; comparing, by a phase detector in the first clock domain, the phases of the first and second clock signals, wherein aligning the phases of the first and second clock signals comprises using the compared phases; and aligning, by a control circuit, the phases of the first and second clock signals by selecting the one of the third clock signals and controlling the phase adjustment of the selected third clock signal.
9. The method of claim 8 , further comprising glitch-less switching, by the coarse DLL, between outputting consecutive ones of the third clock signals.
10. The method of claim 9 , wherein the glitch-less switching comprises blending, by a plurality of pass transistors of the coarse DLL, the consecutive ones of the third clock signals.
11. The method of claim 8 , wherein the control circuit has an unlimited phase acquisition range of the first and second clock signals.
12. The method of claim 8 , wherein there are more than four third clock signals generated by the coarse DLL, the third clock signals are evenly spaced and span the clock period of the first clock signal, and the fine DLL has a phase adjustment range of at least twice and no more than four times the spacing of the third clock signals.
13. The method of claim 8 , wherein the number of third clock signals exceeds the ratio of the speed of the first clock domain to the speed of the second clock domain.
14. The method of claim 8 , further comprising: dividing the first clock signal by a first clock divider in the first clock domain; and generating, by a second clock divider in the second data circuit, the second clock signal by dividing the fourth clock signal; wherein comparing the phases of the first and second clock signals comprises comparing the phase of the divided first clock signal to the phase of the second clock signal.
15. A clock alignment system comprising: a first data circuit configured to operate in a first clock domain; a clock generator in the first clock domain, and configured to generate a first clock signal to drive the first data circuit; a second data circuit configured to operate in a second clock domain slower than the first clock domain by at least a factor of four, the second data circuit further configured to generate a second clock signal and to transfer data to the first data circuit in synchronization with the second clock signal; a coarse delay-locked loop (DLL) configured to generate at least eight third clock signals from the first clock signal, and to output a selected one of the third clock signals, the third clock signals having corresponding evenly spaced phase offsets from the first clock signal that span the clock period of the first clock signal; a fine DLL to generate a fourth clock signal to drive the second data circuit, by adjusting a phase of the selected third clock signal; a phase detector configured to operate in the first clock domain, and further configured to compare the phases of the first and second clock signals; and a control circuit configured to align the phases of the first and second clock signals using the compared phases by selecting the one of the third clock signals and controlling the phase adjustment of the selected third clock signal.
16. The system of claim 15 , wherein the coarse DLL has glitch-less switching between outputting consecutive ones of the third clock signals.
17. The system of claim 16 , wherein the coarse DLL comprises a plurality of pass transistors to blend the consecutive ones of the third clock signals during the glitch-less switching.
18. The system of claim 15 , wherein the control circuit has an unlimited phase acquisition range of the first and second clock signals.
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December 9, 2019
November 17, 2020
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