A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory system comprising: a memory device having a plurality of banks, each bank comprising a memory cell region including a plurality of memory cells, a control logic circuit, a data input/output unit, an internal buffer, and a page buffer unit, wherein the internal buffer corresponds to the page buffer unit in each bank, and is the same size as the page buffer unit in each bank; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device so that during the write operation the write data received by the control logic circuit from the controller is transmitted to the page buffer unit and the internal buffer by the data input/output circuit according to an input/output control signal, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks, wherein the PBT has a plurality of fields corresponding to the number of the banks, and each of the fields has a size corresponding to a size of the page buffer unit in each of the banks; and a processor suitable for controlling the memory device to write one of the write data and data stored in the page buffer unit to memory cells selected according to the write address by comparing the write data to data stored in a field of the PBT, the field corresponding to the write address, wherein the processor controls the memory device to write the data stored in the page buffer unit to memory cells to skip a buffer operation between the controller and the page buffer unit, by the control logic circuit generating the input/output control signal to disable the input/output unit when the write data is identical to the data stored in the field of the PBT, otherwise, the control logic circuit generates the input/output control signal to control the input/output unit to transmit the write data received from the controller to the page buffer unit and the internal buffer so that the page buffer unit and the internal buffer store the write data, and the processor selects the field of the PBT according to the write address, and updates the selected field with the write data.
2. The memory system of claim 1 , wherein the processor comprises: a comparison module suitable for comparing the write data to the data stored in the field of the PBT, and outputting a comparison signal; and a management module suitable for controlling the memory device to write the data stored in the page buffer unit to the selected memory cells when the comparison signal indicates that the data are same, and controlling the memory device to write the write data to the selected memory cells when the comparison signal indicates that the data are different from each other.
3. The memory system of claim 1 , wherein the controller receives a read address from the host, and controls a read operation of the memory device, and wherein, when data read from memory cells selected according to the read address are same as the data stored in the page buffer unit, the memory device does not output the data read from the selected memory cells, but provides a match signal to the controller.
4. The memory system of claim 3 , wherein the match signal comprises 1-bit data.
5. The memory system of claim 3 , wherein, during the read operation, the controller outputs data stored in a field of the PBT, corresponding to the read address, as read data to the host in response to the match signal.
6. The memory system of claim 3 , wherein the controller outputs the match signal instead of read data to the host, during the read operation.
7. The memory system of claim 3 , wherein, when the data read from the selected memory cells are different from the data stored in the page buffer unit during the read operation, the memory device outputs the data read from the selected memory cells as read data, and the controller outputs the read data to the host, selects the field of the PBT according to the read address, and updates the selected field to the read data.
8. The memory system of claim 1 , wherein, during the read operation, the memory device stores the data read from the selected memory cells into the page buffer unit, and compares the data stored in the page buffer unit to the data stored in the internal buffer.
9. The memory system of claim 1 , wherein the controller further comprises: a scheduler suitable for receiving the write address and the write data from the host, and performing scheduling to write the same write data to the same bank.
10. The memory system of claim 1 , wherein each of the fields of the PBT is selected according to an address containing rank information, bank group information and bank information.
11. The memory system of claim 1 , wherein the PBT comprises a static random access memory (SRAM).
12. An operation method of a memory system, comprising: providing a memory device having a plurality of banks, each bank including a memory cell region including a plurality of memory cells, a control logic circuit, a data input/output unit, an internal buffer, and a page buffer unit, wherein the internal buffer corresponds to the page buffer unit in each bank, and is the same size as the page buffer unit in each bank; and providing a controller including a page buffer table (PBT) having fields to retain the same data as the page buffer units of the respective banks, wherein the PBT has a plurality of fields corresponding to the number of the banks, and each of the fields has a size corresponding to a size of the page buffer unit in each of the banks; receiving a write address and write data from a host, wherein during a write operation the write data received by the control logic circuit from the controller is transmitted to the page buffer unit and the internal buffer by the data input/output unit according to an input/output control signal; outputting a comparison signal by comparing the write data to data stored in a field of the PBT, the field corresponding to the write address; writing data stored in the page buffer unit to memory cells selected according to the write address to skip a buffer operation between the controller and the page buffer unit, by generating the input/output control signal to disable the input/output unit when the comparison signal indicates that the data are same; and writing the write data to the selected memory cells and generating the input/output control signal to control the input/output unit to transmit the write data received from the controller to the page buffer unit and the internal buffer so that the page buffer unit and the internal buffer store the write data when the comparison signal indicates that the data are different from each other.
13. The operation method of claim 12 , further comprising: selecting the field of the PBT according to the write address, and updating the selected field to the write data, when the comparison signal indicates that the data are different from each other.
14. The operation method of claim 12 , further comprising: performing scheduling to write the same write data to the same bank.
15. An operation method of a memory system, comprising: providing a memory device having a plurality of banks, each bank including a memory cell region including a plurality of memory cells, an internal buffer, and a page buffer unit, wherein the internal buffer corresponds to the page buffer unit in each bank, and is the same size as the page buffer unit in each bank; and providing a controller including a page buffer table (PBT) having fields to retain the same data as the page buffer units of the respective banks, wherein the PBT has a plurality of fields corresponding to the number of the banks, and each of the fields has a size corresponding to a size of the page buffer unit in each of the banks; receiving a read address from a host; reading data from a memory cell according to the read address; storing the data which is read in the page buffer unit; comparing, by the memory device, data in the page buffer unit to data stored in the internal buffer from a last operation; outputting, by the memory device, a match signal to the controller without outputting the data read from the page buffer unit to skip a buffer operation between the controller and the page buffer unit, when a comparison result indicates that the data are same; and outputting, by the memory device, the data read from the page buffer unit as read data to the controller, and storing the data stored in the page buffer unit into the internal buffer so that the internal buffer can retain the same data as the page buffer unit, when the comparison result indicates that the data are different from each other.
16. The operation method of claim 15 , further comprising: selecting, by the controller, a field of the PBT according to the read address, and updating the selected field to the read data, when the comparison result indicates that the data are different from each other.
17. The operation method of claim 15 , wherein the match signal comprises 1-bit data.
18. The operation method of claim 15 , wherein the controller outputs data stored in a field of the PBT, corresponding to the read address, as the read data to the host in response to the match signal.
19. The operation method of claim 15 , wherein the controller outputs the match signal instead of the read data to the host.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 18, 2018
November 24, 2020
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