A processor includes a processing engine, an address queue, an address generation unit, and logic circuitry. The processing engine is configured to process instructions that access data in an external memory. The address generation unit is configured to generate respective addresses for the instructions to be processed by the processing engine, to provide the addresses to the processing engine, and to write the addresses to the address queue. The logic circuitry is configured to access the external memory on behalf of the processing engine while compensating for variations in access latency to the external memory, by reading the addresses from the address queue, and executing the instructions in the external memory in accordance with the addresses read from the address queue.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processor, comprising: a vector processing engine; and a scalar processor, which is configured to: fetch, from a memory, Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots; extract scalar instructions from the scalar-instruction slots of the VLIW instructions, and execute the scalar instructions; extract, from the vector-instruction slots of the VLIW instructions, vector instructions comprising read and write instructions that access data in the memory; pre-process the vector instructions, including: generating addresses for use by the vector processing engine in accessing the data; storing the generated addresses in an address queue; and accessing the memory on behalf of the vector processing engine while compensating for variations in access latency to the memory, by reading the addresses from the address queue and executing the vector instructions in the memory in accordance with the addresses read from the address queue; and transfer the pre-processed vector instructions to the vector processing engine for execution.
2. The processor according to claim 1 , wherein the vector instructions comprise write instructions for writing data to the memory, wherein the vector processing engine is configured to write the data to a data buffer, and wherein the scalar processor is configured to write the data from the data buffer to the memory.
3. The processor according to claim 1 , wherein the vector instructions comprise read instructions for reading data from the memory, and wherein the scalar processor is configured to read the data from the memory into a data buffer, to be available to the vector processing engine.
4. A processor, comprising: a vector processing engine; and a scalar processor, which is configured to: fetch, from a memory, Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots; extract scalar instructions from the scalar-instruction slots of the VLIW instructions, and execute the scalar instructions; and extract, from the vector-instruction slots of the VLIW instructions, vector instructions comprising read instructions for reading data from the memory; pre-process the vector instructions, including: requesting the data from the memory in a first order; receiving the data from the memory into a data buffer in a second order that is different from the first order, but providing the data to the vector processing engine, using the data buffer, in the first order; and transfer the pre-processed vector instructions to the vector processing engine for execution.
5. The processor according to claim 1 , wherein the scalar processor is configured to store data, which is associated with the vector instructions, in an instruction queue, so as to provide the vector instructions to the vector processing engine in synchronization with the data.
6. A processor, comprising: a vector processing engine; and a scalar processor, which is configured to: fetch, from a memory, Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots; extract scalar instructions from the scalar-instruction slots of the VLIW instructions, and execute the scalar instructions; extract vector instructions from the vector-instruction slots of the VLIW instructions, pre-process the vector instructions, and transfer the pre-processed vector instructions to the vector processing engine for execution; and two or more counters that are allocated to respective kernels processed by the vector processing engine, wherein each counter is configured to count write operations to the memory that were requested by the scalar processor but not yet completed, and wherein, when one of the counters is decremented to zero, the scalar processor is configured to indicate to the vector processing engine that data for the corresponding kernel is ready in the memory.
7. A method in a processor that comprises a scalar processor and a vector processing engine, the method comprising: using the scalar processor: fetching from a memory Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots; extracting scalar instructions from the scalar-instruction slots of the VLIW instructions, and executing the scalar instructions; extracting, from the vector-instruction slots of the VLIW instructions, vector instructions comprising read and write instructions that access data in the memory; pre-processing the vector instructions, including: generating addresses for use by the vector processing engine in accessing the data; storing the generated addresses in an address queue; and accessing the memory on behalf of the vector processing engine while compensating for variations in access latency to the memory, by reading the addresses from the address queue and executing the vector instructions in the memory in accordance with the addresses read from the address queue; and transferring the pre-processed vector instructions to the vector processing engine; and executing the pre-processed vector instructions using the vector processing engine.
8. The method according to claim 7 , wherein extracting the vector instructions comprises extracting write instructions for writing data to the memory, and comprising writing the data by the vector processing engine to a data buffer, and writing the data from the data buffer to the memory by the scalar processor.
9. The method according to claim 7 , wherein extracting the vector instructions comprises extracting read instructions for reading data from the memory, and wherein pre-processing the vector instructions comprises reading the data from the memory into a data buffer, to be available to the vector processing engine.
10. A method in a processor that comprises a scalar processor and a vector processing engine, the method comprising: using the scalar processor: fetching from a memory Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots; extracting scalar instructions from the scalar-instruction slots of the VLIW instructions, and executing the scalar instructions; and extracting, from the vector-instruction slots of the VLIW instructions, vector instructions comprising read instructions for reading data from the memory; pre-processing the vector instructions, including: requesting the data from the memory in a first order; receiving the data from the memory into a data buffer in a second order that is different from the first order, but providing the data to the vector processing engine, using the data buffer, in the first order; and transferring the pre-processed vector instructions to the vector processing engine; and executing the pre-processed vector instructions using the vector processing engine.
11. The method according to claim 7 , wherein pre-processing the vector instructions comprises storing data, which is associated with the vector instructions, in an instruction queue, so as to provide the vector instructions to the vector processing engine in synchronization with the data.
12. A method in a processor that comprises a scalar processor and a vector processing engine, the method comprising: using the scalar processor: fetching from a memory Very Long Instruction Word (VLIW) instructions that comprise both scalar-instruction slots and vector-instruction slots; extracting scalar instructions from the scalar-instruction slots of the VLIW instructions, and executing the scalar instructions; and extracting vector instructions from the vector-instruction slots of the VLIW instructions, pre-processing the vector instructions and transferring the pre-processed vector instructions to the vector processing engine; executing the pre-processed vector instructions using the vector processing engine; and allocating two or more counters to respective kernels processed by the vector processing engine, counting in each counter write operations to the memory that were requested by the scalar processor but not yet completed, and, when one of the counters is decremented to zero, indicating by the scalar processor to the vector processing engine that data for the corresponding kernel is ready in the memory.
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October 3, 2018
December 1, 2020
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