A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of erasing memory cells of a nonvolatile semiconductor memory device that comprises: a memory string including a first transistor, a second transistor, and a plurality of memory cells provided along a first direction and between the first transistor and the second transistor, and stacked above a semiconductor substrate; a plurality of first word lines electrically connected to the memory string; and a plurality of second word lines electrically connected to the memory string, said method comprising an erasing operation and a verifying operation, wherein during the erasing operation, a first voltage is applied to the first word lines, a second voltage, which is lower than the first voltage, to the second word lines, and an erasing voltage, which is higher than the first voltage, to one end of the memory string, and during the verifying operation, substantially the same voltage is applied to the first word lines and the second word lines.
2. The method according to claim 1 , wherein the memory string includes a plurality of zones.
3. The method according to claim 2 , wherein the first word lines and the second word lines belong to different zones.
4. The method according to claim 1 , wherein the nonvolatile semiconductor memory device further comprises a plurality of third word lines electrically connected to the memory string, and wherein during the erasing operation, a third voltage, which is less than the first voltage and greater than the second voltage, is applied to the third word lines, and during the verifying operation, substantially the same voltage is applied to the first word lines, the second word lines, and the third word lines.
5. The method according to claim 4 , wherein the memory string includes a plurality of zones, and the first word lines, the second word lines, and the third word lines belong to different zones.
6. The method according to claim 1 , wherein the semiconductor memory device is a NAND flash memory and each of the plurality of memory cells stores multi-bit data.
7. The method according to claim 1 , wherein the non-volatile semiconductor memory device further comprises a bit line and a source line electrically connected to opposite ends of the memory string.
8. A semiconductor memory device comprising: a memory string including a first transistor, a second transistor, and a plurality of memory cells provided along a first direction and between the first transistor and the second transistor, and stacked above a semiconductor substrate; a plurality of first word lines electrically connected to the memory string; a plurality of second word lines electrically connected to the memory string; a control unit configured to perform an erase operation including an erasing operation and a verifying operation, wherein the control unit: during the erasing operation, applies a first voltage to the first word lines, a second voltage, which is lower than the first voltage, to the second word lines, and an erasing voltage, which is higher than the first voltage, to a source, and during the verifying operation, applies substantially the same voltage to the first word lines and the second word lines.
9. The semiconductor memory device according to claim 8 , wherein the memory string includes a plurality of zones.
10. The semiconductor memory device according to claim 9 , wherein the first word lines and the second word lines belong to different zones.
11. The semiconductor memory device according to claim 8 , further comprising: a plurality of third word lines electrically connected to the memory string, wherein the control unit: during the erasing operation, applies a third voltage, which is less than the first voltage and greater than the second voltage, to the third word lines, and during the verifying operation, applies substantially the same voltage to the first word lines, the second word lines, and the third word lines.
12. The semiconductor memory device according to claim 11 , wherein the memory string includes a plurality of zones, and the first word lines, the second word lines, and the third word lines belong to different zones.
13. The semiconductor memory device according to claim 8 , wherein the semiconductor memory device is a NAND flash memory and each of the plurality of memory cells stores multi-bit data.
14. The semiconductor memory device according to claim 8 , further comprising: a bit line and a source line electrically connected to opposite ends of the memory string.
15. A method of erasing memory cells of a nonvolatile semiconductor memory device that comprises: a memory string including a first transistor, a second transistor, and a plurality of memory cells provided along a first direction and between the first transistor and the second transistor, and stacked above a semiconductor substrate; a plurality of first word lines electrically connected to the memory string; and a plurality of second word lines electrically connected to the memory string; said method comprising an erasing operation and a verifying operation, wherein during the erasing operation, a first voltage is applied to the first word lines, a second voltage, which is lower than the first voltage, to the second word lines, and an erasing voltage, which is higher than the first voltage, to a well, and during the verifying operation, substantially the same voltage is applied to the first word lines and the second word lines.
16. The method according to claim 15 , wherein the memory string includes a plurality of zones including first and second zones, and the first word lines belong to the first zone and the second word lines belong to the second zone.
17. The method according to claim 15 , wherein the non-volatile semiconductor memory device further comprises a plurality of third word lines electrically connected to the memory string, and wherein during the erasing operation, a third voltage, which is less than the first voltage and greater than the second voltage, is applied to the third word lines, and during the verifying operation, substantially the same voltage is applied to the first word lines, the second word lines, and the third word lines.
18. The method according to claim 17 , wherein the memory string includes a plurality of zones, and the first word lines, the second word lines, and the third word lines belong to different zones.
19. The method according to claim 15 , wherein the semiconductor memory device is a NAND flash memory and each of the plurality of memory cells stores multi-bit data.
20. The method according to claim 15 , wherein the non-volatile semiconductor memory device further comprises a bit line and a source line electrically connected to opposite ends of the memory string.
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July 1, 2019
December 1, 2020
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