The present disclosure provides a semiconductor IC structure having vertical wire bonding and method of making it. The method includes two steps. First step: providing a semiconductor chip, disposing a first solder joint and a second solder joint separately on its surface, disposing a wire bonding pad at the first solder joint, to connect to an internal functioning device of the semiconductor chip, and disposing a dummy pad at the second solder joint. Second step: bonding a metal wire on the wire bonding pad, cutting the metal wire on the dummy pad, and breaking the metal wire by pulling above the wire bonding pad, to obtain a vertical conductive column connected to the wire bonding pad.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A vertical wire bonding method for a semiconductor IC, comprising the following two steps: step S 1 comprising: providing a semiconductor chip, disposing a first solder joint and a second solder joint separately on a surface of the semiconductor chip, disposing a wire bonding pad at the first solder joint, wherein the wire bonding pad is connected to an internal functioning device of the semiconductor chip, and disposing a dummy pad at the second solder joint; and step S 2 comprising: bonding a metal wire on the wire bonding pad, cutting the metal wire on the dummy pad, and breaking the metal wire by pulling above the wire bonding pad, to obtain a vertical conductive column connected to the wire bonding pad.
2. The vertical wire bonding method according to claim 1 , wherein the step S 2 comprises the following sub-steps: S 2 - 1 : passing the metal wire through a chopper, leaving a safe distance from a chopper head; S 2 - 2 : melting a wire tail of the metal wire into a metal ball; S 2 - 3 : lowering the chopper to the first solder joint, and press-welding the metal ball onto a surface of the wire bonding pad; S 2 - 4 : lifting the chopper after the press-welding is completed; S 2 - 5 : when the chopper is lifted to a height required by wire bonding, closing a wire clamp above the chopper, lowering and moving the chopper to the second solder joint, and thinning the metal wire on a surface of the dummy pad; and S 2 - 6 : moving the chopper to a preset height above the first solder joint, keeping the wire clamp closed, and breaking the metal wire at a thinned location by using an upward pulling force of the chopper.
3. The vertical wire bonding method according to claim 2 , wherein in the step S 2 - 5 , after thinning the metal wire on the surface of the dummy pad, the chopper further performs oscillation in a horizontal direction.
4. The vertical wire bonding method according to claim 1 , wherein the dummy pad has a thickness ranging from 2 μm to 5 μm.
5. The vertical wire bonding method according to claim 1 , wherein an area of a top surface of the dummy pad is greater than an area of a bottom surface of the chopper.
6. The vertical wire bonding method according to claim 5 , wherein the area of the top surface of the dummy pad is 1.1 to 1.5 times of the area of the bottom surface of the chopper.
7. The vertical wire bonding method according to claim 1 , wherein a surface of the semiconductor chip is provided with an insulation layer, and the dummy pad is located on a surface of the insulation layer and is not connected to the internal functioning device of the semiconductor chip.
8. The vertical wire bonding method according to claim 1 , wherein the vertical conductive column is used for three-dimensional packaging.
9. A semiconductor IC structure made by the vertical wire bonding method according to claim 1 .
10. The semiconductor IC structure according to claim 9 , wherein the dummy pad has a thickness ranging from 2 μm to 5 μm.
11. The semiconductor IC structure according to claim 9 , wherein a top surface of the dummy pad is greater than a bottom surface of the chopper.
12. The semiconductor IC structure according to claim 9 , wherein the top surface of the dummy pad is 1.1 to 1.5 times of the bottom surface of the chopper.
13. The semiconductor IC structure according to claim 9 , wherein a surface of the semiconductor chip is provided with an insulation layer, and the dummy pad is located on a surface of the insulation layer and is not connected to the internal functioning device of the semiconductor chip.
14. The semiconductor IC structure according to claim 9 , wherein the vertical conductive column connects the semiconductor chip to a three-dimensional packaging device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 29, 2019
December 1, 2020
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