A sensor is provided to include: a sampling clock circuit generating a sample clock signal with a predetermined sample clock period; a system clock circuit generating a system clock signal with a predetermined system clock period, wherein a value of the system clock period is less than a value of the sample clock period; a sensor circuit generating, during each sample clock period, a sensor signal representing a position of an object; a sampling circuit receiving the sensor signal and generate sample signal value in response; an interpolation circuit determining a first difference between a current sample signal and a previous sample signal, determining a second difference between a switchpoint threshold value and the previous sample signal, and determining a delay count based upon a ratio of the first difference and the second difference; and a switchpoint signal circuit generating a switchpoint signal based upon the delay count.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A magnetic field sensor comprising: a sampling clock circuit configured to: generate a sample clock signal with a predetermined sample clock period; a system clock circuit configured to: generate a system clock signal with a predetermined system clock period, wherein a value of the system clock period is less than a value of the sample clock period; a sensor circuit configured to: generate, during each sample clock period, a sensor signal representing a position of an object; a sampling circuit configured to: receive the sensor signal and generate sample signal value in response thereto; an interpolation circuit configured to: determine a first difference between a current sample signal value and a previous sample signal value; determine a second difference between a switchpoint threshold value and the previous sample signal value; and determine a delay count based upon a ratio of the first difference and the second difference; and a switchpoint signal circuit configured to: generate a switchpoint signal based upon the delay count.
2. The magnetic field sensor of claim 1 , wherein the switchpoint signal circuit is further configured to: start a counter when a fixed duration passes after a detection of a switchpoint, wherein the counter increases for each system clock signal; and generate the switchpoint signal when the counter reaches the delay count.
3. The magnetic field sensor of claim 2 , wherein the fixed duration comprises the predetermined sample clock period.
4. The magnetic field sensor of claim 2 , wherein the fixed duration comprises a number of system clock signals to determine the delay count.
5. The magnetic field sensor of claim 1 , wherein the delay count is determined by multiplying the ratio by a number of system clock signals occurring in a sample clock period and applying a modulo operation to the number of the system clock signals.
6. The magnetic field sensor of claim 1 , wherein the sensor circuit comprises: one or more magnetic field sensors configured to detect an external magnetic field of the object.
7. The magnetic field sensor of claim 1 , wherein the delay count is determined digitally.
8. The magnetic field sensor of claim 1 , wherein the delay count is determined using a formula of: Delay Count = Int ( SC * Threshold Difference Sample Difference Mod ( SC ) ) , in which SC is a number of system clock signals occurring in a sample clock period.
9. A method comprising: generating a sample clock signal with a predetermined sample dock period; generating a system clock signal with a predetermined system clock period, wherein a value of the system clock period is less than a value of the sample dock period; generating, during each sample clock period, a sensor signal representing a position of an object; receiving the sensor signal and generate sample signal value in response thereto; determining a first difference between a current sample signal value and a previous sample signal value; determining a second difference between a switchpoint threshold u the previous sample signal value; determining a delay count based upon a ratio of the first difference and the second difference; and generating a switchpoint signal based upon the delay count.
10. The method of claim 9 further comprising: starting a counter when a fixed duration passes after a detection of a switchpoint, wherein the counter increases for each system dock signal; and generating the switchpoint signal when the counter reaches the delay count.
11. The method of claim 10 , wherein the fixed duration comprises the predetermined sample clock period.
12. The method of claim 10 , wherein e fixed duration comprises a number of system clock signals to determine the delay count.
13. The method of claim 9 , wherein the delay count is determined by multiplying the ratio by a number of system clock signals occurring in a sample clock period and applying a modulo operation to the number of the system clock signals.
14. The method of claim 9 , wherein the delay count is determined using a formula of: Delay Count = Int ( SC * Threshold Difference Sample Difference Mod ( SC ) ) , in which SC is a number of system clock signals occurring in a sample clock period.
15. An apparatus method comprising: means for generating a sample clock signal with a predetermined sample clock period; means for generating a system clock signal with a predetermined system clock period, wherein a value of the system clock period is less than a value of the sample clock period; means for generating, during each sample clock period, a sensor signal representing a position of an object; means for receiving the sensor signal and generating a sample signal value in response thereto; means for determining a first difference between a current sample signal value and a previous sample signal value; means for determining a second difference between a switchpoint threshold value and the previous sample signal value; means for determining a delay count based upon a ratio of the first difference and the second difference; and means for generating a switchpoint signal based upon the delay count.
16. The apparatus of claim 15 further comprising: means for starting a counter when a fixed duration passes after a detection of a switchpoint, wherein the counter increases for each system clock signal; and means for generating the switchpoint signal when the counter reaches the delay count.
17. The apparatus of claim 16 , wherein the fixed duration comprises the predetermined sample clock period.
18. The apparatus of claim 16 , wherein the fixed duration comprises a number of system clock signals to determine the delay count.
19. The apparatus of claim 15 , wherein the delay count is determined by multiplying the ratio by a number of system clock signals occurring in a sample clock period and applying a modulo operation to the number of the system clock signals.
20. The apparatus of claim 15 , wherein the delay count is determined using a formula of: Delay Count = Int ( SC * Threshold Difference Sample Difference Mod ( SC ) ) , in which SC is a number of system clock signals occurring in a sample clock period.
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May 14, 2019
December 15, 2020
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