A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a memory cell; a pair of bit lines coupled to the memory cell; a precharge circuit coupled between the pair of bit lines, wherein the precharge circuit is configured to precharge each of the bit lines to approximately a power rail voltage to begin a write operation; a multiplexer configured to select the pair of bit lines coupled to the memory cell during the write operation and after the precharge circuit is turned off; and a pull-up circuit coupled to the multiplexer, the pull-up circuit configured to: select, after the write operation begins, which one of the pair of bit lines is a non-zero bit line driven to a logic high; and increase a voltage difference between the non-zero bit line and a zero bit line of the pair of bit lines to flip logical states of stored bits by clamping the selected non-zero bit line through the multiplexer to approximately the power rail voltage during the write operation.
2. The apparatus of claim 1 , wherein the multiplexer comprises a pair of write pass transistors each coupled to a different one of the pair of bit lines and a pair of read pass transistors each coupled to a different one of the pair of bit lines, wherein the multiplexer is configured to select the pair of bit lines during the write operation by turning on the pair of write pass transistors and turning on the pair of read pass transistors.
3. The apparatus of claim 2 , wherein the pull-up circuit is coupled to the pair of read pass transistors, wherein the pull-up circuit is configured to: select which one of the pair of bit lines is the non-zero bit line by selecting a one of the pair of read pass transistors that is coupled to the non-zero bit line; and clamp the one selected non-zero bit line to approximately the power rail voltage through the selected one of the pair of read pass transistors.
4. The apparatus of claim 1 , further comprising a write select line and a read select line, wherein: the multiplexer comprises a pair of write pass n-channel field effect transistors (NFETs) and a pair of read pass p-channel field effect transistors (PFETs); the write select line is configured to be asserted when the pair of bit lines are selected for the write operation; the read select line is configured to be unasserted when the pair of bit lines are selected for the write operation; first gates of the pair of write pass NFETs are coupled to the write select line so that the pair of write pass NFETs are turned on when the write select line is asserted; and second gates of the pair of read pass PFETs are coupled to the read select line so that the pair of read pass PFETs are turned on when the read select line is unasserted.
5. The apparatus of claim 4 , wherein the pull-up circuit comprises a first stack of pull-up transistors coupled to a drain of one of the pair of read pass PFETs and a second stack of pull-up transistors coupled to a drain of another one of the pair of read pass PFETs, wherein the pull-up circuit is configured to: select which one of the pair of bit lines is the non-zero bit line by turning on a one of either the first stack of pull-up transistors or the second stack of pull-up transistors that is coupled to the drain of a read pass PFET of the pair of read pass PFETs that is coupled to the non-zero bit line; and clamp the one selected non-zero bit line to approximately the power rail voltage by charging the non-zero bit line to approximately the power rail voltage with the turned on one of the first stack of pull-up transistors or the second stack of pull-up transistors.
6. The apparatus of claim 5 , wherein the first stack of pull-up transistors comprises a first stack of pull-up PFETs and the second stack of pull-up transistors comprises a second stack of pull-up PFETs and, wherein: a first pull-up PFET in the first stack of pull-up PFETs comprising a gate configured to receive a write clock signal; a second pull-up PFET in the first stack of pull-up PFETs comprising a gate configured to receive a global write data signal; a first pull-up PFET in the second stack of pull-up PFETs comprising a gate configured to receive the write clock signal; and a second pull-up PFET in the second stack of pull-up PFETs comprising a gate configured to receive a complementary global write data signal.
7. The apparatus of claim 1 , further comprising sense amplifier input lines that are each coupled through the multiplexer to a different one of the pair of bit lines, the pull-up circuit being configured to select which one of the pair of bit lines is the non-zero bit line by selecting a sense amplifier input line of the sense amplifier input lines coupled to the non-zero bit line.
8. The apparatus of claim 7 , wherein the pull-up circuit is configured to clamp the one selected non-zero bit line through the multiplexer to approximately the power rail voltage by pulling up the selected sense amplifier input line to approximately the power rail voltage.
9. The apparatus of claim 1 , further comprising: sense amplifier input lines that are each coupled through the multiplexer to a different one of the pair of bit lines; isolation transistors that are each coupled to a different one of the sense amplifier input lines, wherein the pull-up circuit is coupled between the isolation transistors and the multiplexer; and a NAND gate configured to turn off the isolation transistors during the write operation and to turn on the isolation transistors during a read operation.
10. The apparatus of claim 9 , wherein the isolation transistors comprise isolation p-channel field effect transistors (PFETs) having gates, wherein the NAND gate is configured to pull up each of the gates so as to turn off the isolation PFETs during the write operation and is configured to pull down each of the gates so as to turn on each of the isolation PFETs during the read operation.
11. The apparatus of claim 10 , wherein the NAND gate comprises an output coupled to each of the gates of the isolation PFETs and, wherein the NAND gate is configured to perform a NAND operation between a write clock signal and a sense enable signal so to generate a control voltage at the output that pulls up each of the gates during the write operation and pulls down each of the gates during the read operation.
12. The apparatus of claim 1 , further comprising: one of a mobile phone, personal digital assistant (PDA), Internet of Things device, desktop computer, laptop computer, palm-sized computer, tablet computer, work station, game console, media player, computer based simulators, and wireless communication attachments for laptops incorporating the memory cell, the pair of bit lines, the multiplexor, and the pull-up circuit.
13. A method of performing a write operation in a memory, comprising: precharging bit lines coupled to a memory cell to approximately a power rail voltage to begin the write operation; after turning off the precharging of the bit lines, selecting a pair of bit lines coupled to the memory cell with a multiplexer during the write operation; selecting, after the write operation begins, which one of the pair of bit lines is a non-zero bit line driven to a logic high; and increasing a voltage difference between the non-zero bit line and a zero bit line of the pair of bit lines to flip logical states of stored bits by clamping the selected non-zero bit line through the multiplexer to approximately the power rail voltage during the write operation.
14. The method of claim 13 , wherein selecting the pair of bit lines during the write operation comprises: turning on a pair of write pass transistors in the multiplexer, wherein the pair of write pass transistors are each coupled to a different one of the pair of bit lines; and turning on a pair of read pass transistors in the multiplexer, wherein the pair of read pass transistors are each coupled to a different one of the pair of bit lines.
15. The method of claim 14 , wherein: selecting which one of the pair of bit lines is the non-zero bit line comprises selecting a one of the pair of read pass transistors that is coupled to the non-zero bit line; and clamping the one selected non-zero bit line to approximately the power rail voltage is through the selected one of the pair of read pass transistors.
16. The method of claim 13 , wherein the multiplexer comprises a pair of write pass n-channel field effect transistors (NFETs), first gates of the pair of write pass NFETs coupled to a write select line, a pair of read pass p-channel field effect transistors (PFETs), and second gates of the pair of read pass PFETs coupled to a read select line and, wherein selecting the pair of bit lines coupled to the memory cell with the multiplexer during the write operation, comprises: turning on the pair of write pass NFETs by asserting the write select line; and turning on the pair of read pass PFETs by unasserting the read select line.
17. The method of claim 16 , wherein a first stack of pull-up transistors is coupled to a drain of one of the pair of read pass PFETs and a second stack of pull-up transistors is coupled to a drain of another one of the pair of read pass PFETs and, wherein: selecting which one of the pair of bit lines is the non-zero bit line comprises turning on a one of either the first stack of pull-up transistors or the second stack of pull-up transistors that is coupled to the drain of a read pass PFET of the pair of read pass PFETs that is coupled to the non-zero bit line; and clamping the one selected non-zero bit line to approximately the power rail voltage comprises charging the non-zero bit line to approximately the power rail voltage with the turned on one of the first stack of pull-up transistors or the second stack of pull-up transistors.
18. The method of claim 17 , wherein the first stack of pull-up transistors comprises a first stack of pull-up PFETs and the second stack of pull-up transistors comprises a second stack of pull-up PFETs and, wherein selecting which one of the pair of bit lines is the non-zero bit line comprises: receiving a write clock signal at a gate of a first pull-up PFET in the first stack of pull-up PFETs; receiving a global write data signal at a gate of a second pull-up PFET in the first stack of pull-up PFETs; receiving the write clock signal at a gate of a first pull-up PFET in the second stack of pull-up PFETs; and receiving a complementary global write data signal at a gate of a second pull-up PFET in the second stack of pull-up PFETs.
19. The method of claim 13 , wherein sense amplifier input lines are each coupled through the multiplexer to a different one of the pair of bit lines and, wherein selecting which one of the pair of bit lines is the non-zero bit line comprises selecting a sense amplifier input line of the sense amplifier input lines coupled to the non-zero bit line.
20. The method of claim 19 , wherein clamping the one selected non-zero bit line through the multiplexer to approximately the power rail voltage comprises pulling up the selected sense amplifier input line to approximately the power rail voltage.
21. The method of claim 13 , wherein sense amplifier input lines are each coupled through the multiplexer to a different one of the pair of bit lines and isolation transistors are each coupled to a different one of the sense amplifier input lines and, wherein the method further comprises turning off the isolation transistors during the write operation with a NAND gate and turning on the isolation transistors during a read operation with the NAND gate.
22. The method of claim 21 , wherein the isolation transistors comprise isolation p-channel field effect transistors (PFETs) having gates and, wherein: turning off the isolation transistors during the write operation with the NAND gate comprises pulling up each of the gates so as to turn off the isolation PFETs with the NAND gate; and turning on the isolation transistors during the read operation with the NAND gate comprises pulling down each of the gates so as to turn on each of the isolation PFETs during the read operation.
23. The method of claim 22 , wherein the NAND gate comprises an output coupled to each of the gates of the isolation PFETs and, wherein pulling up each of the gates during the write operation and pulling down each of the gates during the read operation comprises performing a NAND operation between a write clock signal and a sense enable signal with the NAND gate so to generate a control voltage at the output of the NAND gate.
24. An apparatus for performing a write operation in a memory, comprising: a memory cell; a pair of bit lines coupled to the memory cell; a pair of write pass transistors each coupled to a different one of the pair of bit lines and a pair of read pass transistors each coupled to a different one of the pair of bit lines, wherein the pair of write pass transistors and the pair of read pass transistors are configured to couple to the pair of bit lines in a write operation, and only the pair of read pass transistors is configured to couple to the pair of bit lines in a read operation; sense amplifier input lines that are each coupled to a different one of the pair of read pass transistors; and a pull-up circuit being configured to select a sense amplifier input line of the sense amplifier input lines coupled to a one of the pair of read pass transistors that is coupled to a non-zero bit line of the pair of bit lines during the write operation and clamp the non-zero bit line to approximately a power rail voltage by pulling up the selected sense amplifier input line to approximately the power rail voltage.
25. The apparatus of claim 24 , further comprising: a precharge circuit coupled between the pair of bit lines, wherein the precharge circuit is configured to precharge each of the bit lines to approximately a power rail voltage to begin the write operation; and a pull-up circuit coupled to the pair of read pass transistors, wherein the pull-up circuit is configured to, after the precharge circuit is turned off, select a one of the pair of read pass transistors coupled to a non-zero bit line of the pair of bit lines driven to a logic high after the write operation begins and to increase a voltage difference between the non-zero bit line and a zero bit line of the pair of bit lines to flip logical states of stored bits by clamping the selected non-zero bit line through the one of the pair of read pass transistors to approximately the power rail voltage during the write operation.
26. The apparatus of claim 25 , further comprising a write select line and a read select line, wherein: the pair of write pass transistors are a pair of write pass n-channel field effect transistors (NFETs) and the pair of read pass transistors are a pair of read pass p-channel field effect transistors (PFETs); the write select line is configured to be asserted when the pair of bit lines are selected for the write operation; the read select line is configured to be unasserted when the pair of bit lines are selected for the write operation; first gates of the pair of write pass NFETs are coupled to the write select line so that the pair of write pass NFETs are turned on when the write select line is asserted; and second gates of the pair of read pass PFETs are coupled to the read select line so that the pair of read pass PFETs are turned on when the read select line is unasserted.
27. The apparatus of claim 26 , further comprising a first stack of pull-up transistors coupled to a drain of one of the pair of read pass PFETs and a second stack of pull-up transistors coupled to a drain of another one of the pair of read pass PFETs, wherein the pull-up circuit is configured to: turning on a one of either the first stack of pull-up transistors or the second stack of pull-up transistors that is coupled to the drain of a read pass PFET of the pair of read pass PFETs that is coupled to a non-zero bit line of the pair of bit lines during the write operation; and clamp the non-zero bit line to approximately the power rail voltage by charging the non-zero bit line to approximately the power rail voltage with the turned on one of the first stack of pull-up transistors or the second stack of pull-up transistors.
28. The apparatus of claim 27 , wherein the first stack of pull-up transistors comprises a first stack of pull-up PFETs and the second stack of pull-up transistors comprises a second stack of pull-up PFETs and, wherein: a first pull-up PFET in the first stack of pull-up PFETs comprising a gate configured to receive a write clock signal; a second pull-up PFET in the first stack of pull-up PFETs comprising a gate configured to receive a global write data signal; a first pull-up PFET in the second stack of pull-up PFETs comprising a gate configured to receive the write clock signal; and a second pull-up PFET in the second stack of pull-up PFETs comprising a gate configured to receive a complementary global write data signal.
29. The apparatus of claim 24 , further comprising: isolation transistors that are each coupled to a different one of the sense amplifier input lines, wherein the pull-up circuit is coupled between the isolation transistors and the pair of read pass transistors; and a NAND gate configured to turn off the isolation transistors during the write operation and to turn on the isolation transistors during the read operation.
30. The apparatus of claim 29 , wherein the isolation transistors comprise isolation p-channel field effect transistors (PFETs) having gates, wherein the NAND gate is configured to pull up each of the gates so as to turn off the isolation PFETs during the write operation and is configured to pull down each of the gates so as to turn on each of the isolation PFETs during the read operation.
31. The apparatus of claim 30 , wherein the NAND gate comprises an output coupled to each of the gates of the isolation PFETs and, wherein the NAND gate is configured to perform a NAND operation between a write clock signal and a sense enable signal so to generate a control voltage at the output that pulls up each of the gates during the write operation and pulls down each of the gates during the read operation.
32. The apparatus of claim 25 , further comprising: one of a mobile phone, personal digital assistant (PDA), Internet of Things device, desktop computer, laptop computer, palm-sized computer, tablet computer, work station, game console, media player, computer based simulators, and wireless communication attachments for laptops incorporating the memory cell, the pair of bit lines, and the pull-up circuit.
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October 6, 2017
December 15, 2020
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