An adiabatic logic-in-memory based complementary metal-oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit utilizes an adiabatic logic based pre-charged sense amplifier (PCSA) to recover energy from its output load capacitors. The ALiM CMOS/MTJ includes a non-volatile magnetic-tunnel-junction (MTJ) based memory. The ALiM CMOS/MTJ also includes a dual rail complementary metal-oxide-semiconductor (CMOS) logic that performs logic operations in association with the MTJ, and thereby generates logic outputs based on logic inputs. The ALiM CMOS/MTJ also includes the adiabatic PCSA, which is operatively coupled to the dual rail CMOS logic. The adiabatic logic based PCSA includes PCSA circuitry for which an input is a multi-phase power clock, and a charge recovery circuit having the output load capacitors. The charge recovery circuit is operatively coupled to the PCSA circuitry such that the ALiM CMOS/MTJ circuit uses the power clock to recover energy from the output load capacitors.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An adiabatic logic-in-memory based complementary metal-oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit, comprising: a set of magnetic-tunnel-junctions (MTJs) configured to store non-volatile data; a logic network, comprising the set of MTJs and a set of complementary metal-oxide-semiconductor (CMOS) transistors configured to together perform logic operations so as to generate logic outputs based on logic inputs; and an adiabatic logic based pre-charged sense amplifier (PCSA) operatively coupled to the logic network, the adiabatic logic based PCSA comprising: PCSA circuitry for which an input is a multi-phase power clock, the PCSA circuitry including cross-coupled transistors coupled to a common discharge transistor; charge recovery circuitry, including output load capacitors, wherein the charge recovery circuitry is operatively coupled to the PCSA circuitry such that the ALiM CMOS/MTJ circuit uses the power clock to recover energy from output load capacitors.
2. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as an OR gate.
3. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as an XOR gate.
4. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a NOR gate.
5. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as an XNOR gate.
6. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as an AND gate.
7. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a NAND gate.
8. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a NOT gate.
9. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a MUX gate.
10. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as an inverter logic.
11. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as an encoder logic.
12. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a decoder logic.
13. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a full-adder logic.
14. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a half-adder logic.
15. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a full-subtractor logic.
16. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a half-subtractor logic.
17. The adiabatic logic-in-memory based ALiM CMOS/MTJ circuit of claim 1 , wherein the logic network operates as a D-flip-flop logic.
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July 12, 2018
December 15, 2020
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