Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising a processor comprising one or more processor cores, each of the cores being configurable to execute one or more instructions, each of the cores comprising: an execution unit configured to execute register read and write instructions to read from and/or write to, respectively, a register file comprising a plurality of registers; a hardware structure storing data including: a register write mask storing data that indicates which registers of the register file a current group of instructions will write to, and a register read mask storing data that indicates which registers of the register file a next group of instructions will read; and a control unit configured to control issuing of individual register read and write instructions of the next group of instructions to the execution unit by comparing the register write mask data to the register read mask data and allowing execution of a respective one of the individual register read and write instructions when the register write mask indicates any register the respective individual instruction is dependent on has been written by the current group of instructions.
2. The apparatus of claim 1 , wherein the hardware structure further comprises at least one of the following: a register write mask, a register write vector register, a content addressable memory (CAM), or a lookup table.
3. The apparatus of claim 1 , wherein the data stored in the hardware structure indicates which of the registers will be written to by the core executing at least one of the instructions of the instruction block.
4. The apparatus of claim 1 , wherein the data stored in the hardware structure indicates which of the registers have been written by the core during an instance of executing at least one of the instructions of the instruction block.
5. The apparatus of claim 1 , wherein the data stored in the hardware structure is generated by an instruction decoder that decodes the register read and write instructions.
6. The apparatus of claim 1 , wherein the data stored in the hardware structure is generated by reading write mask data from an instruction header encoded in the instruction block.
7. The apparatus of claim 1 , wherein the write instructions comprise explicit register write instructions.
8. The apparatus of claim 7 , wherein the control unit is further configured to compare write vector register data with write mask data from the hardware structure to determine which of the register write instructions have executed.
9. The apparatus of claim 1 , wherein the control unit is further configured to compare write vector register data with write mask data from the hardware structure to determine that all register write instructions for an instruction block ordered to execute before a next instruction block will execute, and, based on the determination, issue one or more instructions of the instruction block to the execution unit.
10. The apparatus of claim 1 , wherein the control unit is configured to, based on the comparing, control issuing of individual register read and write instructions.
11. An apparatus comprising a processor comprising one or more processor cores, each of the cores being configurable to execute one or more groups of instructions, each of the cores comprising: an execution unit configured to execute register read and write instructions contained in a group of instructions to read from and/or write to, respectively, a register file comprising a plurality of registers; a hardware structure storing data indicative of a relative execution ordering of register read and write instructions within the group of instructions; and a control unit configured to control issuing of register read and write instructions to the execution unit based at least in a part on the hardware structure data, the control unit comprising a counter that is incremented when a register write instruction for a previous group of instructions is executed, and wherein the control unit indicates the group of instructions is ready to execute when the counter reaches a predetermined value for a number of register writes executed in the previous group of instructions.
12. The apparatus of claim 11 , wherein the data stored in the hardware structure is generated by an instruction decoder that decodes the register read and write instructions.
13. The apparatus of claim 11 , wherein the control unit is further configured to compare write vector register data with write mask data from the hardware structure to determine that all register write instructions for an instruction block ordered to execute before a next instruction block will execute, and, based on the determination, issue one or more instructions of the instruction block to the execution unit.
14. A method of operating a processor to execute a current block of instructions comprising a plurality of register access instructions, the method comprising: selecting a register access instruction of the plurality of register access instructions to execute by comparing register write data for a previous block of instructions to a counter that indicates execution status of register access instructions for the current block of instructions; and executing the selected register access instruction.
15. The method of claim 14 , wherein the stored data is stored in a write vector register, and wherein the selecting comprises comparing data from a register write mask encoded in a header of the previous block of instructions to the write vector register data.
16. The method of claim 14 , wherein: the stored data is stored in a write vector register; and the selecting comprises evaluating conditions for one or more predicates in the previous block of instructions and, based on the evaluating, nullifying one or more entries in the write vector registers.
17. The method of claim 14 , wherein the stored data is stored in a write vector register, the method further comprising: comparing the write vector register data to a read mask for the block of instructions, a write mask indicating which instructions of the previous block of instructions have executed; and based on the comparing, stalling execution of a next instruction block by processor.
18. The method of claim 17 , further comprising: based on the comparing, performing one of the following operations: stalling execution of one or more register read instructions in the current instruction block, stalling execution of the current instruction block, initiating execution of a next instruction block, or initiating an exception handler to indicate a register access fault, flushing an instruction block, or waiting for a previous instruction block to begin decoding.
19. The method of claim 14 , wherein the stored data is stored in a write vector register, the method further comprising: executing a register write instruction of the previous block of instructions, the register write instruction being encoded with an identifier of the register being written to; and based on the stored data in the write vector register, executing a register read instruction in the current instruction block.
20. One or more computer readable storage media storing computer-readable instructions that when executed by a block-based processor, cause the processor to perform the method of claim 14 .
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February 1, 2016
December 22, 2020
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