The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory storage device, comprising: a memory cell coupled to a bitline; a write driver configured to provide an input data bit to the bitline; switch circuitry configured to couple the bitline to a data line to pass the input data bit from the bitline to the data line; boost circuitry configured to adjust a potential of the input data bit on the data line to be a potential of the input data bit on the bitline, the boost circuitry including a switching element configured to couple the data line to the bitline to adjust the potential of the input data bit on the data line to be the potential of the input data bit on the bitline; and a sense amplifier configured to read the input data bit from the data line to provide an output data bit.
2. The memory storage device of claim 1 , wherein the boost circuitry is configured to pull-down a voltage of the input data bit on the data line to be a voltage of the input data bit on the bitline.
3. The memory storage device of claim 1 , wherein the boost circuitry is configured to pull-up a voltage of the input data bit on the data line to be a voltage of the input data bit on the bitline.
4. The memory storage device of claim 1 , wherein the memory storage device is configured to operate in a read mode of operation, wherein the switch circuitry is configured to couple the bitline to the data line to pass a stored data bit from the memory cell to the data line in the read mode of operation, wherein the sense amplifier is configured to read the stored data bit from the memory cell from the data line to provide the output data bit in the read mode of operation, and wherein the boost circuitry and the write driver are configured to be deactivated in the read mode of operation.
5. The memory storage device of claim 1 , wherein the memory storage device is configured to operate in a write mode of operation, wherein the write driver is configured to provide the input data bit to the bitline for storage into the memory cell in the write mode of operation, wherein the switch circuitry is configured to decouple the bitline from the data line in the write mode of operation, and wherein the boost circuitry and the sense amplifier are configured to be deactivated in the write mode of operation.
6. The memory storage device of claim 1 , wherein the memory storage device is configured to operate in a bypass mode of operation, wherein the write driver is configured to provide the input data bit to the bitline for storage into the memory cell in the bypass mode of operation, wherein the switch circuitry is configured to couple the bitline to the data line to pass the input data bit from the bitline to the data line in the bypass mode of operation, wherein the boost circuitry is configured to adjust the potential of the input data bit on the data line to be the potential of the input data bit on the bitline in the bypass mode of operation, wherein the sense amplifier is configured to read the input data bit from the data line and to provide the output data bit in the bypass mode of operation, and wherein the memory cell is configured to be deactivated in the bypass mode of operation.
7. Boost circuitry within a memory storage device, comprising: a first logical INVERTER gate configured to perform a first logical inversion operation on an input data bit on a bit line of the memory storage device to provide an output of the first logical INVERTER gate; a first switching element configured to adjust a voltage of an input data bit on a data line of the memory storage device to be a potential level of the output of the first logical INVERTER gate; a second logical INVERTER gate configured to perform a second logical inversion operation on a complimentary input data bit on a complementary bit line of the memory storage device to provide an output of the second logical INVERTER gate; a second switching element configured to adjust a voltage of an input data bit on a complementary data line of the memory storage device to be a potential level of the output of the second logical INVERTER gate; and one or more logic gates configured to: activate the first switching element and the second switching element in response to detecting a presence of the input data bit on the bit line and the complementary input data bit on the complementary bit line and in response to a boost enable control signal being at a first logical value, and deactivate the first switching element and the second switching element in response to not detecting the presence of the input data bit on the bit line and the complementary input data bit on the complementary bit line or in response to the boost enable control signal being at a second logical value different from the first logical value.
8. The boost circuitry of claim 7 , wherein the first switching element and the second switching element comprise: n-type metal-oxide-semiconductor field-effect (NMOS) transistors.
9. The boost circuitry of claim 8 , wherein the one or more logic gates comprise: a first logical NOR gate configured to perform a first logical NOR operation on the input data bit on the bit line and the complementary input data bit on the complimentary bit line to detect the presence of the input data bit on the bit line and the complementary input data bit on the complementary bit line; and a second logical NOR gate configured to perform a second logical NOR operation on an output of the first logical NOR gate and the boost enable control signal to activate or to deactivate the first switching element and the second switching element in response thereto.
10. The boost circuitry of claim 7 , wherein the first switching element and the second switching element comprise: p-type metal-oxide-semiconductor field-effect (PMOS) transistors.
11. The boost circuitry of claim 10 , wherein the one or more logic gates comprise: a logical NOR gate configured to perform a logical NOR operation on the input data bit on the bit line and the complementary input data bit on the complementary bit line to detect the presence of the input data bit on the bit line and the complementary input data bit on the complementary bit line; and a logical NAND gate configured to perform a logical NAND operation on an output of the logical NOR gate and the boost enable control signal to activate or to deactivate the first switching element and the second switching element in response thereto.
12. The boost circuitry of claim 7 , wherein the first switching element and the second switching element comprise: transmission gates.
13. The boost circuitry of claim 12 , wherein the one or more logic gates comprise: a logical NOR gate configured to perform a logical NOR operation on the input data bit on the bit line and the complementary input data bit on the complementary bit line to detect the presence of the input data bit on the bit line and the complementary input data bit on the complementary bit line; and a logical NAND gate configured to perform a logical NAND operation on an output of the logical NOR gate and the boost enable control signal to activate or to deactivate the first switching element and the second switching element in response thereto.
14. A method for operating a memory storage device, the method comprising: receiving an input data bit on a bitline; a first coupling of the bitline to a data line to pass the input data bit from the bitline to the data line; adjusting a potential of the input data bit on the data line to be a potential of the input data bit on the bitline, the adjusting comprising a second coupling of the data line to the bitline to adjust the potential of the input data bit on the data line to be the potential of the input data bit on the bitline; and reading the input data bit from the data line to provide an output data bit.
15. The method of claim 14 , further comprising: deactivating a memory array of the memory storage device.
16. The method of claim 14 , wherein the second coupling comprises: the second coupling of the data line to the bitline to pull-down a voltage of the input data bit on the data line to be a voltage of the input data bit on the bitline.
17. The method of claim 14 , wherein the second coupling comprises: the second coupling of the data line to the bitline to pull-up a voltage of the input data bit on the data line to be a voltage of the input data bit on the bitline.
18. The method of claim 14 , further comprising: writing the input data bit to a memory array of the memory storage device in a write mode of operation; reading the output data bit from the memory array in a read mode of operation; and wherein the second coupling comprises: the second coupling of the data line to the bitline to adjust the potential of the input data bit on the data line to be the potential of the input data bit on the bitline in a bypass mode of operation, the memory array being deactivated in the bypass mode of operation.
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July 3, 2019
December 22, 2020
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